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ORCIDChi-Hsiang Huang 0001
Person information
- affiliation: University of Washington, Processing Systems Laboratory, Seattle, WA, USA
- affiliation (former): National Cheng Kung University, Department of Electrical Engineering, Tainan, Taiwan
Other persons with the same name
- Chi-Hsiang Huang 0002
![[0000-0001-5357-0451]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-5357-0451")
— National Taiwan University College of Medicine, Department of Anesthesiology, Taipei, Taiwan (and 1 more)
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Journal Articles
- 2023
[j4]Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe:
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. IEEE J. Solid State Circuits 58(1): 68-77 (2023)- 2022
- [j3]Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe:
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits 57(1): 90-102 (2022) - 2019
- [j2]Hung-Hsien Wu, Chi-Hsiang Huang, Chia-Ling Wei, Jih-Sheng Lai:
Bidirectional Single-Inductor Dual-Supply Converter With Automatic State-Transition for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 4068-4078 (2019) - 2018
- [j1]Chi-Hsiang Huang, Hung-Hsien Wu, Chia-Ling Wei:
Compensator-Free Mixed-Ripple Adaptive On-Time Controlled Boost Converter. IEEE J. Solid State Circuits 53(2): 596-604 (2018)
Conference and Workshop Papers
- 2022
- [c5]Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe:
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. ISSCC 2022: 1-3 - [c4]Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe:
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. ISSCC 2022: 222-224 - 2021
- [c3]Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe:
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. ISSCC 2021: 416-418 - 2020
- [c2]Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe:
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. VLSI Circuits 2020: 1-2 - [c1]Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe:
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. VLSI Circuits 2020: 1-2
Coauthor Index
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