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@article{DBLP:journals/vlsi/AcciaroN98,
  author       = {Vincenzo Acciaro and
                  Amiya Nayak},
  title        = {Characterization of Catastrophic Faults in Reconfigurable Systolic
                  Arrays},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {2},
  pages        = {143--150},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/79841},
  doi          = {10.1155/1998/79841},
  timestamp    = {Sun, 12 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/AcciaroN98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/AlexanderCGR98,
  author       = {Michael J. Alexander and
                  James P. Cohoon and
                  Joseph L. Ganley and
                  Gabriel Robins},
  title        = {Placement and Routing for Performance-Oriented {FPGA} Layout},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  pages        = {97--110},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/38483},
  doi          = {10.1155/1998/38483},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/AlexanderCGR98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/AndreadisKGT98,
  author       = {Ioannis Andreadis and
                  I. Kokolakis and
                  Antonios Gasteratos and
                  Philippos G. Tsalides},
  title        = {A Stochastic {D/A} Converter Based on a Cellular Automaton Architecture},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {2},
  pages        = {203--210},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/91849},
  doi          = {10.1155/1998/91849},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/AndreadisKGT98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/BusabaLW98,
  author       = {Fadi Busaba and
                  Parag K. Lala and
                  Alvernon Walker},
  title        = {On Self-Checking Design of {CMOS} Circuits for Multiple Faults},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {2},
  pages        = {151--161},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/37237},
  doi          = {10.1155/1998/37237},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/BusabaLW98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/CarchioloMM98,
  author       = {Vincenza Carchiolo and
                  Michele Malgeri and
                  Giuseppe Mangioni},
  title        = {Formal Codesign Methodology with Multistep Partitioning},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {4},
  pages        = {401--423},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/18340},
  doi          = {10.1155/1998/18340},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/CarchioloMM98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ChangH98,
  author       = {Ray{-}I Chang and
                  Pei{-}Yung Hsiao},
  title        = {Macro-Cell Placement for Custom-Chip Design Using Self-Organizing
                  Fuzzy Technique},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {4},
  pages        = {385--399},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/61053},
  doi          = {10.1155/1998/61053},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ChangH98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Cho98,
  author       = {Jun{-}Dong Cho},
  title        = {Guest Editorial},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/23013},
  doi          = {10.1155/1998/23013},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Cho98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/DasGJN98,
  author       = {Sunil R. Das and
                  Nita Goel and
                  Wen{-}Ben Jone and
                  Amiya R. Nayak},
  title        = {Syndrome Signature in Output Compaction for {VLSI} Built-in Self-Test},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {2},
  pages        = {191--201},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/45472},
  doi          = {10.1155/1998/45472},
  timestamp    = {Sun, 12 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/DasGJN98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/DeHonK98,
  author       = {Andr{\'{e}} DeHon and
                  Thomas F. Knight Jr.},
  title        = {High Performance, Point-to-Point, Transmission Line Signaling},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  pages        = {111--129},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/84860},
  doi          = {10.1155/1998/84860},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/DeHonK98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/FarrahiTS98,
  author       = {Amir H. Farrahi and
                  Gustavo E. T{\'{e}}llez and
                  Majid Sarrafzadeh},
  title        = {Exploiting Sleep Mode for Memory Partitioning and Other Applications},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {3},
  pages        = {271--287},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/50491},
  doi          = {10.1155/1998/50491},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/FarrahiTS98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Gebotys98,
  author       = {Catherine H. Gebotys},
  title        = {Optimizing Energy During Systems Synthesis of Computer Intensive Realtime
                  Applications},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {3},
  pages        = {303--320},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/54063},
  doi          = {10.1155/1998/54063},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Gebotys98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/GonzalezZ98,
  author       = {Teofilo F. Gonzalez and
                  Si{-}Qing Zheng},
  title        = {On Ensuring Multilayer Wirability by Stretching Layouts},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {4},
  pages        = {365--383},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/14757},
  doi          = {10.1155/1998/14757},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/GonzalezZ98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/JhangHJ98,
  author       = {Kyoung{-}Son Jhang and
                  Soonhoi Ha and
                  Chu Shik Jhon},
  title        = {Simulated Annealing Approach to Crosstalk Minimization in Gridded
                  Channel Routing},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  pages        = {85--95},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/81296},
  doi          = {10.1155/1998/81296},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/JhangHJ98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/KarafyllidisATT98,
  author       = {Ioannis Karafyllidis and
                  Ioannis Andreadis and
                  Philippos G. Tsalides and
                  Adonios Thanailakis},
  title        = {Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators
                  for {VLSI} Systems},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {2},
  pages        = {177--189},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/87186},
  doi          = {10.1155/1998/87186},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/KarafyllidisATT98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/KarayiannisT98,
  author       = {Dimitrios Karayiannis and
                  Spyros Tragoudas},
  title        = {Clustering Network Modules with Different Implementations for Delay
                  Minimization},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  pages        = {1--13},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/69289},
  doi          = {10.1155/1998/69289},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/KarayiannisT98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/KarayiannisT98a,
  author       = {Dimitrios Karayiannis and
                  Spyros Tragoudas},
  title        = {Timing-Driven Circuit Implementation},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {2},
  pages        = {211--224},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/49145},
  doi          = {10.1155/1998/49145},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/KarayiannisT98a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/KatkooriV98,
  author       = {Srinivas Katkoori and
                  Ranga Vemuri},
  title        = {Architectural Power Estimation Based on Behavior Level Profiling},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {3},
  pages        = {255--270},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/93106},
  doi          = {10.1155/1998/93106},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/KatkooriV98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MandalCG98,
  author       = {Chittaranjan A. Mandal and
                  Partha Pratim Chakrabarti and
                  Sujoy Ghose},
  title        = {Complexity of Scheduling in High Level Synthesis},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {4},
  pages        = {337--346},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/52807},
  doi          = {10.1155/1998/52807},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/MandalCG98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Mehta98,
  author       = {Dinesh P. Mehta},
  title        = {{CLOTH} {MEASURE:} {A} Software Tool for Estimating the Memory Requirements
                  of Corner Stitching Data Structures},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {4},
  pages        = {425--436},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/64716},
  doi          = {10.1155/1998/64716},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Mehta98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/NagR98,
  author       = {Sudip Nag and
                  Kaushik Roy},
  title        = {Performance and Wirability Driven Layout for Row-Based FPGAs},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {4},
  pages        = {353--364},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/57380},
  doi          = {10.1155/1998/57380},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/NagR98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/NajmX98,
  author       = {Farid N. Najm and
                  Michael G. Xakellis},
  title        = {Statistical Estimation of the , Switching Activity in {VLSI} Circuits},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {3},
  pages        = {243--254},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/46819},
  doi          = {10.1155/1998/46819},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/NajmX98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/NajmY98,
  author       = {Farid N. Najm and
                  Gary Yeap},
  title        = {Guest Editorial},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {3},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/42156},
  doi          = {10.1155/1998/42156},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/NajmY98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/NevesF98,
  author       = {Jos{\'{e}} Luis Neves and
                  Eby G. Friedman},
  title        = {Automated Synthesis of Skew-Based Clock Distribution Networks},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  pages        = {31--57},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/72951},
  doi          = {10.1155/1998/72951},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/NevesF98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/PandaN98,
  author       = {Rajendran Panda and
                  Farid N. Najm},
  title        = {Post-Mapping Transformations for Low-Power Synthesis},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {3},
  pages        = {289--301},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/96768},
  doi          = {10.1155/1998/96768},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/PandaN98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RavikumarJ98,
  author       = {C. P. Ravikumar and
                  Hemant Joshi},
  title        = {SCOAP-based Testability Analysis from Hierarchical Netlists},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {2},
  pages        = {131--141},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/32654},
  doi          = {10.1155/1998/32654},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/RavikumarJ98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RavikumarS98,
  author       = {C. P. Ravikumar and
                  Nikhil Sharma},
  title        = {Testability-Driven Layout of Combinational Circuits},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {4},
  pages        = {347--352},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/10193},
  doi          = {10.1155/1998/10193},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/RavikumarS98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SpiegelS98,
  author       = {Gerald Spiegel and
                  Albrecht P. Stroele},
  title        = {Realistic Fault Modeling and Extraction of Multiple Bridging and Break
                  Faults},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {2},
  pages        = {163--176},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/83615},
  doi          = {10.1155/1998/83615},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/SpiegelS98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/TellezS98,
  author       = {Gustavo E. T{\'{e}}llez and
                  Majid Sarrafzadeh},
  title        = {On Rectilinear Distance-Preserving Trees},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  pages        = {15--30},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/26574},
  doi          = {10.1155/1998/26574},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/TellezS98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ThakurCW98,
  author       = {Shashidhar Thakur and
                  Kai{-}Yuan Chao and
                  D. F. Wong},
  title        = {Minimum Crosstalk Vertical Layer Assignment for Three-Layer {VHV}
                  Channel Routing},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  pages        = {73--84},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/34910},
  doi          = {10.1155/1998/34910},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ThakurCW98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/TiwariL98,
  author       = {Vivek Tiwari and
                  Mike Tien{-}Chien Lee},
  title        = {Power Analysis of a 32-bit Embedded Microcontroller},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {3},
  pages        = {225--242},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/89432},
  doi          = {10.1155/1998/89432},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/TiwariL98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/VerdierZ98,
  author       = {Fran{\c{c}}ois Verdier and
                  Bertrand Y. Zavidovique},
  title        = {A High Level Synthesis System for {VLSI} Image Processing Applications},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {4},
  pages        = {321--336},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/95421},
  doi          = {10.1155/1998/95421},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/VerdierZ98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/VittalM98,
  author       = {Ashok Vittal and
                  Malgorzata Marek{-}Sadowska},
  title        = {Power Distribution Synthesis for {VLSI}},
  journal      = {{VLSI} Design},
  volume       = {7},
  number       = {1},
  pages        = {59--72},
  year         = {1998},
  url          = {https://doi.org/10.1155/1998/76525},
  doi          = {10.1155/1998/76525},
  timestamp    = {Mon, 08 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/VittalM98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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