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ORCIDJun Yao 0001
Person information
- affiliation: Huawei Technologies Co. Ltd., Beijing, China
- affiliation (former): Nara Institute of Science and Technology, Graduate School of Information Science, Ikoma, Japan
- affiliation (former): Kyoto University, Graduate School of Informatics, Japan
Other persons with the same name
- Jun Yao — disambiguation page
- Jun Yao 0002
![[0000-0002-8885-8698]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-8885-8698")
— Tsinghua University, School of Life Sciences, State Key Laboratory of Biomembrane and Membrane Biotechnology, Beijing, China - Jun Yao 0003 — Chinese University of Hong Kong
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2010 – 2019
- 2015
[j7]Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. IEICE Trans. Inf. Syst. 98-D(12): 2141-2149 (2015)- [c12]Anna Zhang, Jun Yao, Yasuhiko Nakashima:
Lowering the complexity of k-means clustering by BFS-dijkstra method for graph computing. COOL Chips 2015: 1-3 - [c11]Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
A CGRA-Based Approach for Accelerating Convolutional Neural Networks. MCSoC 2015: 73-80 - 2014
- [j6]Yukihiro Sasagawa, Jun Yao, Yasuhiko Nakashima:
Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults. IEICE Trans. Inf. Syst. 97-D(12): 3083-3091 (2014) - [j5]Jun Yao, Yasuhiko Nakashima, Naveen Devisetti, Kazuhiro Yoshimura, Takashi Nakada:
A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction. IEICE Trans. Inf. Syst. 97-D(12): 3092-3100 (2014) - [j4]Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka:
A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor. IEEE Micro 34(6): 54-63 (2014) - [c10]Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka:
A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit. COOL Chips 2014: 1-3 - [c9]Yuttakon Yuttakonkit, Jun Yao, Yasuhiko Nakashima:
A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration. COOL Chips 2014: 1-3 - [c8]Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. CANDAR 2014: 388-393 - 2013
- [j3]Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima:
Selective Check of Data-Path for Effective Fault Tolerance. IEICE Trans. Inf. Syst. 96-D(8): 1592-1601 (2013) - [c7]Wei Wang, Jun Yao, Youhui Zhang, Wei Xue, Yasuhiko Nakashima, Weimin Zheng:
HW/SW approaches to accelerate GRAPES in an FU array. COOL Chips 2013: 1-3 - 2012
- [j2]Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima:
RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2319-2329 (2012) - [c6]Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima:
Introducing OVP awareness to achieve an efficient permanent defect locating. NANOARCH 2012: 43-49 - 2011
- [j1]Kazuhiro Yoshimura, Takuya Iwakami, Takashi Nakada, Jun Yao, Hajime Shimada, Yasuhiko Nakashima:
An Instruction Mapping Scheme for FU Array Accelerator. IEICE Trans. Inf. Syst. 94-D(2): 286-297 (2011) - [c5]Jun Yao, Ryoji Watanabe, Kazuhiro Yoshimura, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima:
An efficient and reliable 1.5-way processor by fusion of space and time redundancies. DSN Workshops 2011: 69-74 - [c4]Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima:
LAPP: A Low Power Array Accelerator with Binary Compatibility. IPDPS Workshops 2011: 854-862 - 2010
- [c3]Jun Yao, Hajime Shimada, Kazutoshi Kobayashi:
A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability. IWIA 2010: 21-29 - [c2]Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi:
A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. PRDC 2010: 237-238
2000 – 2009
- 2005
- [c1]Jun Yao, Hajime Shimada, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita:
Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption. ISHPC 2005: 494-507
Coauthor Index
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