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2010 – 2019
- 2012
[j4]Xu Bai, Nobuaki Okada, Michitaka Kameyama:
A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme. J. Multiple Valued Log. Soft Comput. 20(1-2): 1-18 (2012)- 2010
- [j3]Nobuaki Okada, Michitaka Kameyama:
Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits. IEICE Trans. Inf. Syst. 93-D(8): 2126-2133 (2010) - [c4]Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals. ISMVL 2010: 179-184
2000 – 2009
- 2009
- [c3]Nobuaki Okada, Michitaka Kameyama:
Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. ISMVL 2009: 54-59 - 2008
- [j2]Nobuaki Okada, Michitaka Kameyama:
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation. IEICE Trans. Electron. 91-C(9): 1437-1443 (2008) - [c2]Nobuaki Okada, Michitaka Kameyama:
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. ISMVL 2008: 180-185 - 2007
- [j1]Nobuaki Okada, Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. J. Multiple Valued Log. Soft Comput. 13(4-6): 619-632 (2007) - [c1]Nobuaki Okada, Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. ISMVL 2007: 25
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