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ORCID1. Great Lakes Symposium on VLSI 1991: Kalamazoo, MI, USA
- First Great Lakes Symposium on VLSI, 1991, Kalamazoo, MI, USA, March 1-2, 1991. IEEE 1991, ISBN 0-8186-2170-2
- Jacob A. Abraham:
Design and evaluation of fault tolerance techniques for highly parallel architectures. - Fredrick J. Hill:
Interlocked test generation and digital hardware synthesis. 2-6 - Joseph F. JáJá:
VLSI routing on the pipelined hypercube and related networks. 7-11 - Michael A. Langston, Siddharthan Ramachandramurthi:
Dense layouts for series-parallel circuits. 14-17 - Sourav Bhattacharya, Wei-Tek Tsai:
Area efficient binary tree layout. 18-24 - Charles C. Chiang:
On wiring overlap layouts. 25-30 - Sourav Bhattacharya, Yoon-Hwa Choi, Wei-Tek Tsai:
I/O bound binary tree layout. 31-36 - Kevin T. Kornegay
, Robert W. Brodersen:
A test controller board for TSS. 38-42 - Pier Luca Montessoro, Silvano Gai:
General and efficient multiple list traversal for concurrent fault simulation. 43-48 - Pier Luca Montessoro:
An innovative user interface for fault simulation systems. 49-53 - Antonio Lioy, Massimo Poncino:
A hierarchical multi-level test generation system. 54-59 - A. Duksu Oh, Hyeong-Ah Choi, Abdol-Hossein Esfahanian:
On the complexity of a fault-tolerance model for multicomputer systems. 62-67 - Subramanian Mahalingham, Subra Ganesan:
Algorithm independent data flow mapping on a unified VLSI architecture. 68-73 - A. Deb, Nam Ling:
A massively parallel and versatile architecture for computer vision. 74-79 - M. Starkey, Tony M. Carter:
Transforming disfigured and disoriented areas into routable switchboxes. 82-87 - Teofilo F. Gonzalez, Mohammadreza Razzazi:
On the generalized channel definition problem. 88-91 - Lixin Tao, Yongchang Zhao, Krishnaiyan Thulasiraman, M. N. Shanmukha Swamy:
An efficient tabu search algorithm for graph bisectioning. 92-95 - Norbert Wehn, Manfred Glesner:
A new approach to timing driven partitioning of combinational logic. 96-101 - K. S. Manjunath, Sterling R. Whitaker:
Optimal test set for stuck-at faults in VLSI. 104-109 - K. S. Manjunath, Damu Radharkrishnan:
Transition count testing of CMOS combinational circuits. 110-114 - Antonio Lioy, Enrico Macii, Angelo Raffaele Meo, Matteo Sonza Reorda:
An algebraic approach to test generation for sequential circuits. 115-120 - John A. Canaris, Sterling R. Whitaker:
A low power CMOS correlator. 122-127 - N. Misra, Ashok K. Goel:
Implementation of fault-tolerant sequential circuits using programmable logic arrays. 128-131 - Peter Poechmueller, G. K. Sharma, Manfred Glesner:
A CAD tool for designing large, fault-tolerant VLSI arrays. 132-137 - Hans-Jürgen Herpel, Peter Windirsch, Manfred Glesner, J. Führer, J. Busshardt:
A VLSI implementation of a state variable filter algorithm. 138-143 - Susanne E. Hambrusch, Hung-Yi Tu:
A framework for 1-D compaction with forbidden region avoidance [VLSI layout]. 146-151 - Forbes D. Lewis, Wang Chia-Chi Pong, Nancy K. Van Cleave:
A linear-time heuristic for rectilinear Steiner trees. 152-156 - Dee Parks, Miroslaw Truszczynski:
Routing non-convex grids without holes. 157-162 - Tuang-Kuang Wu, Martin L. Brady:
Four layer wiring using adjacent-layer vias. 163-168 - M. A. AbuZaid, P. V. Vithalani, W. M. Gosney, L. L. Howard, Guenter W. Gross:
A VLSI peripheral system for monitoring and stimulating action potentials of cultured neurons. 170-175 - Chinchuan Chiu, Michael A. Shanblatt:
An architecture design using VLSI building blocks for dynamic programming neural networks. 176-181 - Pong P. Chu:
Applying Hopfield network to find the minimum cost coverage of a Boolean function. 182-185 - E. R. Khan, Nam Ling:
Two-dimensional multirate systolic array design for artificial neural networks. 186-193 - S. G. Burns:
High frequency analog circuit design using QuickChip. 196-201 - Changhyun Kim, D. Kang, Richard B. Brown, Kensall D. Wise:
A high resolution current stimulating probe for use in neural prostheses. 202-206 - Chang N. Zhang, Alen George Law, Ali Rezazadeh:
Designing VLSI systolic arrays with complex processing elements. 207-212 - K. D. Powers, Donna J. Brown, Martin L. Brady:
The 60° grid: routing channels in width d/√3. 214-219 - Ahsan Abdullah, Sarma Sastry:
Topological via minimization and routing. 220-224 - Jill David, Fillia Makedon, Bruno Codenotti, Mauro Leoncini:
An experimental environment for design and analysis of global routing heuristics. 225-230 - Shoichiro Yamada, Hirohisa Tanabe:
Building block layout based on block compaction and two-adjacent-side channel router. 231-236 - Hassan A. Farhat, H. Saidian:
Testability profile estimation of VLSI circuits from fault coverage. 238-242 - Thomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia:
Test plan generation and concurrent scheduling of tests in the presence of conflicts. 243-248 - S. Srinivas, Anupam Basu, Arogyaswami Paulraj, Lalit M. Patnaik:
A parallel algorithm for logic simulation on transputer networks. 249-254 - Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda:
Proving finite state machines correct with an automaton-based method. 255-258 - Jeong-A Lee, Kiseon Kim:
Discrete Fourier transform processors using CORDIC. 260-265 - Sourav Bhattacharya, Yoon-Hwa Choi, Wei-Tek Tsai:
Uni-directional cube-connected cycles. 266-271 - T. Ramesh:
A poly to active region VLSI mask alignment test structure. 278-283 - Peter Poechmueller, Manfred Glesner:
An approach for multilevel logic cell optimization in module generators. 284-289 - Shigeki Yamada, Kazuhiro Yamazaki:
Gate matrix layout based on hierarchical net-list representations. 290-295 - N. Baha, M. Beddiaf, A.-K. Gadiri:
GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics. 296-300 - John A. Canaris:
Schematic driven layout for the custom VLSI design environment. 302-306 - Michael R. Wick, B. D. Britt:
A reconstructive approach to automated design synthesis. 307-311 - Ram Vemuri, Ranga Vemuri:
Genetic synthesis: performance-driven logic synthesis using genetic evolution. 312-317 - D. Buehler, Sterling R. Whitaker, John A. Canaris:
Sequence invariant state machine compiler. 318-323 - Lyle Albertson, Sterling R. Whitaker, R. Merrell:
CMOS output buffer waveshaping. 326-327 - Wei Xu, Ashok K. Goel:
Modeling of the transverse delays in modulation-doped heterojunction field-effect transistors. 328-329 - Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya:
Gate level representation of ECL circuits for fault modeling. 330-331 - Ashok K. Goel, Fritz L. Schuermeyer:
'NCHIPSIM'-a microcomputer simulator of NMOS chip performance indicators. 332-333 - Ihab E. Talkhan, Hoda S. Abdel-Aty-Zohdy:
Evaluation of silicon-on-sapphire enhancement JFETs for digital applications. 334-335 - A. N. Gupte, Ashok K. Goel:
Study of quaternary logic versus binary logic. 336-337 - V. Bobin, Sterling R. Whitaker:
Design of fail-safe CMOS logic circuits. 338-339 - Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia:
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. 340-341 - Peter Poechmueller, Michael Held, Norbert Wehn, Manfred Glesner:
HADES-high-level architecture development and exploration system. 342-343
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