"Integrated approach to area-time tradeoff for built-in-self-test in VLSI ..."

Anupam Basu et al. (1991)

> Home

Details and statistics

DOI: 10.1109/GLSV.1991.143994

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/BasuWBM91
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/BasuWBM91
Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia:
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. Great Lakes Symposium on VLSI 1991: 340-341

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.