default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID27th ARCS 2014: Lübeck, Germany - Workshops
- Walter Stechele, Thomas Wild:
ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering. VDE Verlag / IEEE Xplore 2014, ISBN 978-3-8007-3579-2 - Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. 1-8 - Farhad Mohammadian:
FALP: A Fault Adaptive and Low Power Method for Network on Chip Router. 1-7 - Yangzhao Yang, Naijie Gu, Kaixin Ren, Bingqing Hu:
An Approach to Enhance Loop Performance for Multicluster VLIW DSP Processor. 1-8 - Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour:
Improving Efficiency of Embedded Multi-core Platforms with Scratchpad Memories. 1-8 - Sascha Roloff, Frank Hannig, Jürgen Teich:
Towards Actor-oriented Programming on PGAS-based Multicore Architectures. 1-2 - Peter Waszecki, Martin Lukasiewycz, Samarjit Chakraborty:
Multi-Objective Diagnosis of Non-Permanent Faults in Many-Core Systems. 1-8 - Alexander Biewer, Jens Gladigau, Christian Haubelt:
Towards Tight Interaction of ASP and SMT Solving for System-Level Decision Making. 1-7 - Anna M. Westhoff:
Hybrid parallelization of a seeded region growing segmentation of brain images for a GPU cluster. 1-8 - Johannes Hofmann, Jan Treibig, Georg Hager, Gerhard Wellein:
Performance Engineering for a Medical Imaging Application on the Intel Xeon Phi Accelerator. 1-8 - Ioannis Zgeras, Jürgen Brehm, Michael Knoppik:
PBA2CUDA - A Framework for Parallelizing Population Based Algorithms Using CUDA. 1-6 - Erik Hansson, Erik Alnervik, Christoph W. Keßler, Martti Forsell:
A Quantitative Comparison of PRAM based Emulated Shared Memory Architectures to Current Multicore CPUs and GPUs. 1-7 - Tobias Fleig, Oliver Mattes, Wolfgang Karl:
Evaluation of Adaptive Memory Management Techniques on the Tilera TILE-Gx Platform. 1-8 - Martin Flehmig, Kim Feldhoff, Ulf Markwardt:
ScaFES: An Open-Source Framework for Explicit Solvers Combining High-Scalability with User-Friendliness. 1-8 - Peter Sobe, Peter Schumann:
A Perfomance Study of Parallel Cauchy Reed/Solomon Coding. 1-6 - Steffen Christgau, Johannes Spazier, Bettina Schnor, Martin Hammitzsch, Andrey Y. Babeyko, Joachim Waechter:
A comparison of CUDA and OpenACC: Accelerating the Tsunami Simulation EasyWave. 1-5 - Fabian Nowak, Michael Bromberger, Wolfgang Karl:
An Architecture Framework for Porting Applications to FPGAs. 1-7 - Andreas C. Döring:
Experimental Generation of Configurable Circuits for Rotationally Symmetric Functions. 1-5 - Fabian Nowak:
Evaluating the Energy Efficiency of Reconfigurable Computing Toward Heterogeneous Multi-Core Computing. 1-6 - Gerrit Anders, Alexander Schiendorfer, Jan-Philipp Steghöfer, Wolfgang Reif:
Robust Scheduling in a Self-Organizing Hierarchy of Autonomous Virtual Power Plants. 1-8 - Kirstie L. Bellman, Christopher Landauer:
Reflection Processes Help Integrate Simultaneous Self-Optimization Processes. 1-5 - Nizar Msadek, Rolf Kiefhaber, Theo Ungerer:
Simultaneous Self-Configuration with Multiple Managers for Organic Computing Systems. 1-7 - Sven Tomforde, Jörg Hähner, Hella Seebach, Wolfgang Reif, Bernhard Sick, Arno Wacker, Ingo Scholtes:
Engineering and Mastering Interwoven Systems. 1-8 - Daniel Münch, Michael Paulitsch, Andreas Herkersdorf:
Temporal Separation for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using PCIe SR-IOV. 1-7 - Onur Derin, Leandro Fiorin:
Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors. 1-8 - JongBeom Lim, Daeyong Jung, Taeweon Suh, Heon-Chang Yu:
Unstructured Membership Management for Byzantine Fault Tolerance in Clouds. 1-8 - Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. 1-5
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-12 23:01 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
