Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDJournal of Electronic Testing, Volume 9
Volume 9, Numbers 1-2, August 1996
- Vishwani D. Agrawal:
Editorial. 5 - Bozena Kaminska, Bernard Courtois:
Guest editorial. 7-8 - J. van Spaandonk, Tom A. M. Kevenaar:
Selecting measurements to test the functional behavior of analog circuits. 9-18 - Aigars Gertners, Valery Zagursky, Dzintra Saldava:
Behavior model of mixed ADC systems. 19-27 - Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
A unified approach for fault simulation of linear mixed-signal circuits. 29-41 - Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets. 43-57 - Abdessatar Abderrahman, Bozena Kaminska, Eduard Cerny:
Optimization-based multifrequency test generation for analog circuits. 59-73 - José Machado da Silva, José Silva Matos, Ian M. Bell, Gaynor E. Taylor:
Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits. 75-88 - Javier Argüelles, Salvador Bracho:
Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current. 89-107 - Johan Verfaillie, Didier Haspeslagh:
A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI. 109-115 - Christian Dufaza, Hassan Ihs:
A BIST-DFT technique for DC test of analog modules. 117-133 - Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
Unified built-in self-test for fully differential analog circuits. 135-151 - Yingquan Zhou, Mike W. T. Wong, Yinghua Min:
Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis. 153-163 - J. Raczkowycz, S. Allott, T. I. Pritchard:
A data optimization test technique for characterizing embedded ADCs. 165-175 - Adel Belhaouane, Yvon Savaria, Bozena Kaminska, Daniel Massicotte:
Reconstruction method for jitter tolerant data acquisition system. 177-185 - Andrzej Materka
, Michal Strzelecki:
Parametric testing of mixed-signal circuits by ANN processing of transient responses. 187-202 - Firas Mohamed, Meryem Marzouki:
Test and diagnosis of analog circuits: When fuzziness can lead to accuracy. 203-216
Volume 9, Number 3, December 1996
- Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta:
Fault macromodeling and a testing strategy for opamps. 225-235 - Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar:
Initialization issues in asynchronous circuit synthesis. 237-250 - Mark G. Karpovsky, Vyacheslav N. Yarmolik:
Transparent random access memory testing for pattern sensitive faults. 251-266 - Chen-Pin Kung, Chen-Shang Lin:
Parallel sequence fault simulation for synchronous sequential circuits. 267-277 - D. A. Pierce, Parag K. Lala:
Modular implementation of efficient self-checking checkers for the Berger code. 279-294 - Josep Rius, Joan Figueras:
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. 295-310 - Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang:
Cell delay fault testing for iterative logic arrays. 311-316
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-05-06 21:16 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
