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Publication search results
found 17 matches
- 2004
- Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan:
An analysis of a resource efficient checkpoint architecture. ACM Trans. Archit. Code Optim. 1(4): 418-444 (2004) - Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli:
Removing communications in clustered microarchitectures through instruction replication. ACM Trans. Archit. Code Optim. 1(2): 127-151 (2004) - Yu Bai, R. Iris Bahar:
A low-power in-order/out-of-order issue queue. ACM Trans. Archit. Code Optim. 1(2): 152-179 (2004) - Brad Calder, Dean M. Tullsen:
Introduction. ACM Trans. Archit. Code Optim. 1(1): 1-2 (2004) - Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez:
Toward kilo-instruction processors. ACM Trans. Archit. Code Optim. 1(4): 389-417 (2004) - Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn:
Interaction cost and shotgun profiling. ACM Trans. Archit. Code Optim. 1(3): 272-304 (2004) - Allan Hartstein, Thomas R. Puzak:
The optimum pipeline depth considering both power and performance. ACM Trans. Archit. Code Optim. 1(4): 369-388 (2004) - Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin:
Datapath and control for quantum wires. ACM Trans. Archit. Code Optim. 1(1): 34-61 (2004) - Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras:
Implementing branch-predictor decay using quasi-static memory cells. ACM Trans. Archit. Code Optim. 1(2): 180-219 (2004) - Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan:
A compiler framework for speculative optimizations. ACM Trans. Archit. Code Optim. 1(3): 247-271 (2004) - Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore:
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. ACM Trans. Archit. Code Optim. 1(1): 62-93 (2004) - Karthik Sankaranarayanan, Kevin Skadron:
Profile-based adaptation for cache decay. ACM Trans. Archit. Code Optim. 1(3): 305-322 (2004) - Oliverio J. Santana, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero:
A low-complexity fetch architecture for high-performance superscalar processors. ACM Trans. Archit. Code Optim. 1(2): 220-245 (2004) - Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang, Sivakumar Velusamy, David Tarjan:
Temperature-aware microarchitecture: Modeling and implementation. ACM Trans. Archit. Code Optim. 1(1): 94-125 (2004) - Fen Xie, Margaret Martonosi, Sharad Malik:
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. ACM Trans. Archit. Code Optim. 1(3): 323-367 (2004) - Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee:
Tolerating memory latency through push prefetching for pointer-intensive applications. ACM Trans. Archit. Code Optim. 1(4): 445-475 (2004) - Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Reducing instruction cache energy consumption using a compiler-based strategy. ACM Trans. Archit. Code Optim. 1(1): 3-33 (2004)
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