• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 34 matches

• 1997
• 
  Michael J. Alexander:
  Power optimization for FPGA look-up tables. ISPD 1997: 156-162
• 
  Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan:
  Faster minimization of linear wirelength for global placement. ISPD 1997: 4-11
• 
  C. Douglass Bateman, Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky:
  Provably good routing tree construction with multi-port terminals. ISPD 1997: 96-102
• 
  A. Bertolet, K. Carpenter, Keith M. Carrig, Albert M. Chu, A. Dean, Frank D. Ferraiolo, Stephan Kenyon, D. Phan, John G. Petrovick, G. Rodgers, D. Willmott, T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. Andrew Scott, Richard J. Weiss:
  A pseudo-hierarchical methodology for high performance microprocessor design. ISPD 1997: 124-129
• 
  Jeffrey L. Burns, Jack A. Feldman:
  C5M - a control logic layout synthesis system for high-performance microprocessors. ISPD 1997: 110-115
• 
  R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele:
  Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. ISPD 1997: 212-217
• 
  Raul Camposano:
  The quarter micron challenge: intergrating physical and logic design. ISPD 1997: 211
• 
  Young-Jun Cha, Chong S. Rim, Kazuo Nakajima:
  A simple and effective greedy multilayer router for MCMs. ISPD 1997: 67-72
• 
  Jun Dong Cho:
  A min-cost flow based min-cost rectilinear Steiner distance-preserving tree construction. ISPD 1997: 82-87
• 
  Chris C. N. Chu, D. F. Wong:
  A matrix synthesis approach to thermal placement. ISPD 1997: 163-168
• 
  Chris C. N. Chu, D. F. Wong:
  Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD 1997: 192-197
• 
  Jason Cong, Andrew B. Kahng, Kwok-Shing Leung:
  Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. ISPD 1997: 88-95
• 
  Jason Cong, Patrick H. Madden:
  Performance driven global routing for standard cell design. ISPD 1997: 73-80
• 
  Parthasarathi Dasgupta, Susmita Sur-Kolay:
  Slicibility of rectangular graphs and floorplan optimization. ISPD 1997: 150-155
• 
  Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez:
  A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation. ISPD 1997: 116-121
• 
  Glenn Holt, Akhilesh Tyagi:
  Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis. ISPD 1997: 48-53
• 
  T. C. Hu:
  Physical design: mathematical models and methods. ISPD 1997: 207-210
• 
  Dennis J.-H. Huang, Andrew B. Kahng:
  Partitioning-based standard-cell global placement with an exact objective. ISPD 1997: 18-25
• 
  Nevin Kapur, Debabrata Ghosh, Franc Brglez:
  Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. ISPD 1997: 136-143
• 
  Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi:
  EWA: exact wiring-sizing algorithm. ISPD 1997: 178-185
• 
  Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy:
  The future of logic synthesis and physical design in deep-submicron process geometries. ISPD 1997: 218-224
• 
  Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar:
  Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD 1997: 130-135
• 
  Ernest S. Kuh:
  Physical design: reminiscing and looking ahead. ISPD 1997: 206
• 
  David P. LaPotin, Uttam Ghoshal, Eli Chiprout, Sani R. Nassif:
  Physical design challenges for performance. ISPD 1997: 225-226
• 
  Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic:
  On two-step routing for FPGAS. ISPD 1997: 60-66
• 
  Huiqun Liu, D. F. Wong:
  Network flow based multi-way partitioning with area and pin constraints. ISPD 1997: 12-17
• 
  Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko:
  VLSI/PCB placement with obstacles based on sequence-pair. ISPD 1997: 26-31
• 
  R. X. T. Nijssen, C. A. J. van Eijk:
  Regular layout generation of logically optimized datapaths. ISPD 1997: 42-47
• 
  Louis Scheffer:
  A roadmap of CAD tool changes for sub-micron interconnect problems. ISPD 1997: 104-109
• 
  Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes:
  Timing driven placement in interaction with netlist transformations. ISPD 1997: 36-41

skipping 4 more matches