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Publication search results
found 101 matches
- 2016
- Mohamed S. Abdelfattah, Vaughn Betz:
LYNX: CAD for FPGA-based networks-on-chip. FPL 2016: 1-10 - Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel:
FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs. FPL 2016: 1-4 - Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz:
Measure twice and cut once: Robust dynamic voltage scaling for FPGAs. FPL 2016: 1-11 - Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2 - Konstantinos Boikos, Christos-Savvas Bouganis:
Semi-dense SLAM on an FPGA SoC. FPL 2016: 1-4 - Jose Canilho, Mário P. Véstias, Horácio C. Neto:
Multi-core for K-means clustering on FPGA. FPL 2016: 1-4 - Ren Chen, Viktor K. Prasanna:
Optimizing interconnection complexity for realizing fixed permutation in data and signal processing algorithms. FPL 2016: 1-9 - Kumar H. B. Chethan, Nachiket Kapre:
Hoplite-DSP: Harnessing the Xilinx DSP48 multiplexers to efficiently support NoCs on FPGAs. FPL 2016: 1-10 - Jungwook Choi, Rob A. Rutenbar:
Configurable and scalable belief propagation accelerator for computer vision. FPL 2016: 1-4 - Jacob Couch, John Arkoian:
An investigation into a circuit based supply chain analyzer for FPGAs. FPL 2016: 1-9 - Baptiste Delporte, Anthony Convers, Roberto Rigamonti, Alberto Dassatti:
Transparent FPGA flow. FPL 2016: 1 - Daniel C. Dinis, Rui Fiel Cordeiro, Arnaldo S. R. Oliveira, José M. N. Vieira:
Towards an all-digital antenna array transmitter. FPL 2016: 1-2 - Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser:
Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers. FPL 2016: 1-4 - Esam El-Araby, Nader M. Namazi:
Chaotic architectures for secure free-space optical communication. FPL 2016: 1-5 - Nina Engelhardt, Hayden Kwok-Hay So:
GraVF: A vertex-centric distributed graph processing framework on FPGAs. FPL 2016: 1-4 - Xitian Fan, Huimin Li, Wei Cao, Lingli Wang:
DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications. FPL 2016: 1-9 - Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang:
HeteroSim: A heterogeneous CPU-FPGA simulator. FPL 2016: 1 - Daniel Fenzandez, Carlos González, Daniel Mozos:
Dimensionality reduction of hyperspectral images using reconfigurable hardware. FPL 2016: 1-2 - Hugo Fernandes, M. Awais Aslam, Jorge Lobo, João Filipe Ferreira, Jorge Dias:
Bayesian inference implemented on FPGA with stochastic bitstreams for an autonomous robot. FPL 2016: 1-4 - Pietro Fezzardi, Fabrizio Ferrandi:
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers. FPL 2016: 1-9 - Ilya Ganusov, Benjamin Devlin:
Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs. FPL 2016: 1-9 - Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das:
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. FPL 2016: 1-10 - Heiner Giefers, Peter W. J. Staar, Raphael Polig:
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA. FPL 2016: 1-9 - Jeffrey Goeders, Steven J. E. Wilton:
Quantifying observability for in-system debug of high-level synthesis circuits. FPL 2016: 1-11 - Paul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer J. Sherwin:
Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA. FPL 2016: 1-9 - Ammon Gruwell, Peter Zabriskie, Michael J. Wirthlin:
High-speed programmable FPGA Configuration through JTAG. FPL 2016: 1-4 - Chin Hau Hoo, Yajun Ha, Akash Kumar:
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. FPL 2016: 1-11 - Pierre-Henri Horrein, Benoit Porteboeuf, André Lalevee:
Ouessant: Microcontroller approach for flexible accelerator integration and control in System-on-Chip. FPL 2016: 1-4 - Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto:
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4 - Christophe Huriaux, Olivier Sentieys, Russell Tessier:
Effects of I/O routing through column interfaces in embedded FPGA fabrics. FPL 2016: 1-9
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