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Publication search results
found 67 matches
- 2005
- Nisar Ahmed, Mohammad Tehranipoor:
Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. DFT 2005: 187-198 - Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda:
Should Illinois-Scan Based Architectures be Centralized or Distributed? DFT 2005: 406-414 - Sadeka Ali, Gregory Briggs, Martin Margala:
A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test. DFT 2005: 591-600 - Hossein Asadi, Mehdi Baradaran Tahoori:
Soft Error Modeling and Protection for Sequential Elements. DFT 2005: 463-474 - Siavash Bayat Sarmadi, M. Anwar Hasan:
Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme. DFT 2005: 102-110 - Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT 2005: 445-453 - Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto:
A model of soft error effects in generic IP processors. DFT 2005: 334-342 - Luca Breveglieri, Israel Koren, Paolo Maistri:
Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard. DFT 2005: 72-80 - Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A Self Checking Reed Solomon Encoder: Design and Analysis. DFT 2005: 111-119 - Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
FPGA oriented design of parity sharing RS codecs. DFT 2005: 259-265 - G. Cellere, Alessandro Paccagnella, Angelo Visconti, Mauro Bonanomi:
Soft Errors induced by single heavy ions in Floating Gate memory arrays. DFT 2005: 275-284 - Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali:
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems. DFT 2005: 158-168 - Glenn H. Chapman, Israel Koren, Zahava Koren, Jozsef Dudas, Cory Jung:
On-Line Identification of Faults in Fault-Tolerant Imagers. DFT 2005: 149-157 - In Suk Chong, Antonio Ortega:
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms. DFT 2005: 523-534 - Hyukjune Chung, Antonio Ortega:
Analysis and Testing for Error Tolerant Motion Estimation. DFT 2005: 514-522 - Jia Di, Parag K. Lala, Dilip P. Vasudevan:
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT 2005: 371-379 - Mahdi Fazeli, Reza Farivar, Seyed Ghassem Miremadi:
A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems. DFT 2005: 266-274 - Masaru Fukushi, Yusuke Fukushima, Susumu Horiguchi:
A Genetic Approach for the Reconfiguration of Degradable Processor Arrays. DFT 2005: 63-71 - Roberto Gómez, Alejandro Girón, Víctor H. Champac:
Test of Interconnection Opens Considering Coupling Signals. DFT 2005: 247-258 - Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh:
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. DFT 2005: 238-246 - Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis:
Software-Based Self-Test for Pipelined Processors: A Case Study. DFT 2005: 535-543 - David M. Horan, Richard A. Guinee:
A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences. DFT 2005: 229-237 - Cory Jung, Mohammad Hadi Izadi, Michelle L. La Haye:
Noise Analysis of Fault Tolerant Active Pixel Sensors. DFT 2005: 140-148 - Haruhiko Kaneko:
Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment. DFT 2005: 93-101 - Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi:
On the Modeling and Analysis of Jitter in ATE Using Matlab. DFT 2005: 285-293 - Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi:
Data Dependent Jitter (DDJ) Characterization Methodology. DFT 2005: 294-304 - Masato Kitakami, Manabu Sueishi:
Fault-Tolerant Wormhole Switching with Backtracking Capability. DFT 2005: 505-513 - Jeetendra Kumar, Mehdi Baradaran Tahoori:
A Low Power Soft Error Suppression Technique for Dynamic Logic. DFT 2005: 454-462 - Jinkyu Lee, Nur A. Touba:
Low Power BIST Based on Scan Partitioning. DFT 2005: 33-41 - Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic:
Securing Scan Design Using Lock and Key Technique. DFT 2005: 51-62
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