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Publication search results
found 112 matches
- 1995
- R. Dean Adams, John Connor, Garret S. Koch, Luigi Ternullo Jr.:
A 370-MHz memory built-in self-test state machine. ED&TC 1995: 139-143 - Peter Altenbernd:
Deadline-monotonic software scheduling for the co-synthesis of parallel hard real-time systems. ED&TC 1995: 190-197 - David L. Andrews
, Andrew Wheeler, Barry Wealand, Cliff Kancler:
Rapid prototype of a hardware emulator for a SIMD processor array. ED&TC 1995: 391-397 - J. Soares Augusto
, C. F. Beltrá Almeida:
Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosis. ED&TC 1995: 605 - Bechir Ayari, Naim Ben-Hamida, Bozena Kaminska:
Automatic test vector generation for mixed-signal circuits. ED&TC 1995: 458-463 - Alessandro Balboni, Claudio Costi, A. Pellencin, M. Quadrini, Donatella Sciuto:
Automatic clock tree generation in ASIC designs. ED&TC 1995: 351-357 - Bernd Becker, Rolf Drechsler:
How many decomposition types do we need? [decision diagrams]. ED&TC 1995: 438-443 - Bernd Becker
, Rolf Drechsler
:
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams. ED&TC 1995: 592 - D. A. Bensouiah, R. J. Mack, R. E. Massara:
Integration of an expert system for analogue layout synthesis into a commercial CAD framework. ED&TC 1995: 591 - Alessandro Bogliolo, Maurizio Damiani:
Synthesis of multilevel fault-tolerant combinational circuits. ED&TC 1995: 80-85 - J.-M. Bourguet, T. Nancy, Shao-Jun Wei, Jacques Leroy, Raymond Crappe:
A variant of Cooley-Tuckey algorithm with local memory management. ED&TC 1995: 7-11 - G. Van Brakel, Uwe Gläser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus:
Gate delay fault test generation for non-scan circuits. ED&TC 1995: 308-313 - A. H. Bratt, Andrew Mark David Richardson
, R. J. A. Harvey, A. P. Dorey:
A design-for-test structure for optimising analogue and mixed signal IC test. ED&TC 1995: 24-33 - Joan Carletta, Christos A. Papachristou:
A method for testability analysis and BIST insertion at the RTL. ED&TC 1995: 600 - Albert E. Casavant:
Balancing structural hazards and hardware cost of pipelined processors. ED&TC 1995: 562-567 - Pascal Caunegre, Claude Abraham:
Achieving simulation-based test program verification and fault simulation capabilities for mixed-signal systems. ED&TC 1995: 469-479 - Ing-Yi Chen, Geng-Lin Chen, Sy-Yen Kuo:
Delay models for the sea-of-wires array synthesis system. ED&TC 1995: 228-233 - Fulvio Corno, Marco Cusinato, Mario Ferrero, Paolo Prinetto:
Proving testing preorders for process algebra descriptions. ED&TC 1995: 333-339 - Fulvio Corno
, Paolo Prinetto, Matteo Sonza Reorda
:
Using symbolic techniques to find the maximum clique in very large sparse graphs. ED&TC 1995: 320-324 - Fulvio Corno
, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
:
GARDA: a diagnostic ATPG for large synchronous sequential circuits. ED&TC 1995: 267-273 - Jesus Crespo, F. Calvo, Juan I. Solana, Rafael Caravantes, J. L. Conesa:
TRJM: a high speed programmable ATM-SDH mapper. ED&TC 1995: 589 - Dominique Dallet, Giovanni Franco, Philippe Marchegay, Carlo Morandi:
A comparative study of algorithms for A/D converter performance evaluation by statistical analysis. ED&TC 1995: 606 - Marcello Dalpasso
, Michele Favalli, Piero Olivo:
Correlation between IDDQ testing quality and sensor accuracy. ED&TC 1995: 568-572 - Mario Diaz-Nava, Didier Belot, P. Delerue, Joseph Bulone:
A 622/155 mbps ATM line terminator mono-chip. ED&TC 1995: 173-179 - Rolf Drechsler
, Bernd Becker
:
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. ED&TC 1995: 91-99 - E. Driouk, O. Jarov, A. Sukhodolsky:
On software development to support statistical simulation of analogue circuits. ED&TC 1995: 539-543 - Christian Dufaza, H. Viallon, Cyril Chevalier:
BIST hardware generator for mixed test scheme. ED&TC 1995: 424-430 - George-Peter K. Economou, John Ant. Hallas, Evaggelinos P. Mariatos, Constantinos E. Goutis:
Artificial neural networks in medical decision making systems: an application to pulmonary diseases' diagnosis through VHDL synthesis. ED&TC 1995: 590 - Andreas Fauth, Johan Van Praet, Markus Freericks:
Describing instruction set processors using nML. ED&TC 1995: 503-507 - Michele Favalli, Bruno Riccò, L. Penza:
A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs. ED&TC 1995: 599
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retrieved on 2024-07-23 15:35 CEST from data curated by the dblp team
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