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Publication search results
found 175 matches
- 2007
- Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet Meiling Wang:
Delay Uncertainty Reduction by Interconnect and Gate Splitting. ASP-DAC 2007: 690-695 - Ameya R. Agnihotri, Patrick H. Madden:
Fast Analytic Placement using Minimum Cost Flow. ASP-DAC 2007: 128-134 - Imran Ahmed, Tughrul Arslan:
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond. ASP-DAC 2007: 589-594 - Charbel J. Akl, Magdy A. Bayoumi:
Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects. ASP-DAC 2007: 696-701 - Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda:
Systematic Scan Reconfiguration. ASP-DAC 2007: 738-743 - Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud:
Frequency Selective Model Order Reduction via Spectral Zero Projection. ASP-DAC 2007: 379-383 - Roy Armoni, Limor Fix, Ranan Fraer, Tamir Heyman, Moshe Y. Vardi, Yakir Vizel, Yael Zbar:
Deeper Bound in BMC by Combining Constant Propagation and Abstraction. ASP-DAC 2007: 304-309 - Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty
, Vikram Iyengar:
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ASP-DAC 2007: 823-828 - Subhasis Banerjee, G. Surendra, S. K. Nandy:
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC 2007: 884-889 - Swarup Bhunia
, Massood Tabib-Azar
, Daniel G. Saab:
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ASP-DAC 2007: 86-91 - Marc Boule, Zeljko Zilic:
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. ASP-DAC 2007: 324-329 - Zhen Cao, Tong Jing, Jinjun Xiong
, Yu Hu, Lei He, Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC 2007: 256-261 - Michael Chan, Adam Postula, Yong Ding:
PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool. ASP-DAC 2007: 74-79 - Pramod Chandraiah, Junyu Peng, Rainer Dömer:
Creating Explicit Communication in SoC Models Using Interactive Re-Coding. ASP-DAC 2007: 50-55 - Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Safe Delay Optimization for Physical Synthesis. ASP-DAC 2007: 628-633 - Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Fixing Design Errors with Counterexamples and Resynthesis. ASP-DAC 2007: 944-949 - Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang
:
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534 - Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai:
DFM/DFY practices during physical designs for timing, signal integrity, and power. ASP-DAC 2007: 232-237 - Jian-Jia Chen
, Kazuo Iwama, Tei-Wei Kuo
, Hsueh-I Lu:
Flow Time Minimization under Energy Constraints. ASP-DAC 2007: 866-871 - Jian-Jia Chen
, Chuan-Yue Yang, Tei-Wei Kuo
, Chi-Sheng Shih
:
Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems. ASP-DAC 2007: 342-349 - Ruiming Chen, Hai Zhou:
Fast Buffer Insertion for Yield Optimization Under Process Variations. ASP-DAC 2007: 19-24 - Ruiming Chen, Hai Zhou:
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. ASP-DAC 2007: 462-467 - Siddharth Choudhuri, Tony Givargis:
System Architecture for Software Peripherals. ASP-DAC 2007: 56-61 - Min-Lun Chuang, Chun-Yao Wang:
Synthesis of Reversible Sequential Elements. ASP-DAC 2007: 420-425 - Jason Cong, Guojie Luo, Jie Wei, Yan Zhang:
Thermal-Aware 3D IC Placement Via Transformation. ASP-DAC 2007: 780-785 - S. Dabas, Ning Dong, Jaijeet S. Roychowdhury:
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. ASP-DAC 2007: 361-366 - Liang Deng, Martin D. F. Wong
, Kai-Yuan Chao, Hua Xiang:
Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC 2007: 13-18 - Soumyajit Dey, Monu Kedia, Anupam Basu:
Architectural Optimizations for Text to Speech Synthesis in Embedded Systems. ASP-DAC 2007: 298-303 - Stefan Disch, Christoph Scholl:
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets. ASP-DAC 2007: 938-943 - Yazhuo Dong, Yong Dou:
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications. ASP-DAC 2007: 523-528
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