- Doron Drusinsky-Yoresh:
Symbolic cover minimization of fully I/O specified finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 779-781 (1990) - Pierre-François Dubois, Alain Puissochet, Anne-Marie Tagant:
A general and flexible switchbox router: CARIOCA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1307-1317 (1990) - F. Joel Ferguson:
Detection of multiple faults in MOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 1009-1014 (1990) - Hideo Fujiwara, Tomoo Inoue:
Optimal granularity of test generation in a distributed system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 885-892 (1990) - Sanae Fukuda, Naoyuki Shigyo, Koichi Kato, Shin Nakamura:
A ULSI 2-D capacitance simulator for complex structures based on actual processes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 39-47 (1990) - Joel W. Gannett:
SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 669-674 (1990) - Gert Goossens, Jan M. Rabaey, Joos Vandewalle, Hugo De Man:
An efficient microcode compiler for application specific DSP processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 925-937 (1990) - Patrick Groeneveld:
A multiple layer contour-based gridless channel router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1278-1288 (1990) - Gertjan J. Hemink, Berend W. Meijer, Hans G. Kerkhoff:
Testability analysis of analog systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 573-583 (1990) - Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong:
Pad minimization for planar routing of multiple power nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 419-426 (1990) - Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong:
Layer assignment for multichip modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1272-1277 (1990) - Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong:
New algorithms for the rectilinear Steiner tree problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 185-193 (1990) - Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, J. Will Specks:
Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 236-247 (1990) - Pei-Yung Hsiao, Wu-Shiung Feng:
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 522-536 (1990) - Yu Hen Hu, Sao-Jie Chen
:
GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 836-845 (1990) - Wei-Kang Huang, Yinan N. Shen, Fabrizio Lombardi:
New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 323-328 (1990) - Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu:
A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 781-786 (1990) - TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Exploiting communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 1017-1027 (1990) - Nagisa Ishiura, Masayuki Ito, Shuzo Yajima:
Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 868-875 (1990) - Razali Ismail
, Gehan A. J. Amaratunga:
Adaptive meshing schemes for simulating dopant diffusion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 276-289 (1990) - Kazuhiko Iwasaki, Fumio Arakawa:
An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 427-438 (1990) - Vijay S. Iyengar, Barry K. Rosen, John A. Waicukauski:
On computing the sizes of detected delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 299-312 (1990) - Navneet K. Jain, V. C. Prasad, A. B. Bhattacharyya:
Delay time sensitivity in nonlinear monotone RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 554-560 (1990) - Niraj K. Jha:
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 332-336 (1990) - Michael Kaufmann:
A linear-time algorithm for routing in a convex grid. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 180-184 (1990) - Han Young Koh, Carlo H. Séquin, Paul R. Gray:
OPASYN: a compiler for CMOS operational amplifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 113-125 (1990) - Yue-Sun Kuo:
Representing large cell maps. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(11): 1238-1241 (1990) - Sunggu Lee, Kang G. Shin:
Design for test using partial parallel scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 203-211 (1990) - David M. Lewis:
Device model approximation using 2N trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 30-38 (1990) - Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni:
Long and short covering edges in combination logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1245-1253 (1990)