- 1998
- Vincenzo Acciaro, Amiya Nayak
:
Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays. VLSI Design 7(2): 143-150 (1998) - Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins:
Placement and Routing for Performance-Oriented FPGA Layout. VLSI Design 7(1): 97-110 (1998) - Ioannis Andreadis, I. Kokolakis, Antonios Gasteratos, Philippos G. Tsalides:
A Stochastic D/A Converter Based on a Cellular Automaton Architecture. VLSI Design 7(2): 203-210 (1998) - Fadi Busaba, Parag K. Lala, Alvernon Walker:
On Self-Checking Design of CMOS Circuits for Multiple Faults. VLSI Design 7(2): 151-161 (1998) - Vincenza Carchiolo
, Michele Malgeri, Giuseppe Mangioni:
Formal Codesign Methodology with Multistep Partitioning. VLSI Design 7(4): 401-423 (1998) - Ray-I Chang, Pei-Yung Hsiao:
Macro-Cell Placement for Custom-Chip Design Using Self-Organizing Fuzzy Technique. VLSI Design 7(4): 385-399 (1998) - Jun-Dong Cho:
Guest Editorial. VLSI Design 7(1) (1998) - Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak
:
Syndrome Signature in Output Compaction for VLSI Built-in Self-Test. VLSI Design 7(2): 191-201 (1998) - André DeHon, Thomas F. Knight Jr.:
High Performance, Point-to-Point, Transmission Line Signaling. VLSI Design 7(1): 111-129 (1998) - Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh:
Exploiting Sleep Mode for Memory Partitioning and Other Applications. VLSI Design 7(3): 271-287 (1998) - Catherine H. Gebotys:
Optimizing Energy During Systems Synthesis of Computer Intensive Realtime Applications. VLSI Design 7(3): 303-320 (1998) - Teofilo F. Gonzalez, Si-Qing Zheng:
On Ensuring Multilayer Wirability by Stretching Layouts. VLSI Design 7(4): 365-383 (1998) - Kyoung-Son Jhang
, Soonhoi Ha, Chu Shik Jhon:
Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing. VLSI Design 7(1): 85-95 (1998) - Ioannis Karafyllidis
, Ioannis Andreadis, Philippos G. Tsalides, Adonios Thanailakis:
Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems. VLSI Design 7(2): 177-189 (1998) - Dimitrios Karayiannis, Spyros Tragoudas:
Clustering Network Modules with Different Implementations for Delay Minimization. VLSI Design 7(1): 1-13 (1998) - Dimitrios Karayiannis, Spyros Tragoudas:
Timing-Driven Circuit Implementation. VLSI Design 7(2): 211-224 (1998) - Srinivas Katkoori, Ranga Vemuri
:
Architectural Power Estimation Based on Behavior Level Profiling. VLSI Design 7(3): 255-270 (1998) - Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose:
Complexity of Scheduling in High Level Synthesis. VLSI Design 7(4): 337-346 (1998) - Dinesh P. Mehta
:
CLOTH MEASURE: A Software Tool for Estimating the Memory Requirements of Corner Stitching Data Structures. VLSI Design 7(4): 425-436 (1998) - Sudip Nag, Kaushik Roy:
Performance and Wirability Driven Layout for Row-Based FPGAs. VLSI Design 7(4): 353-364 (1998) - Farid N. Najm, Michael G. Xakellis:
Statistical Estimation of the , Switching Activity in VLSI Circuits. VLSI Design 7(3): 243-254 (1998) - Farid N. Najm, Gary Yeap:
Guest Editorial. VLSI Design 7(3) (1998) - José Luis Neves, Eby G. Friedman:
Automated Synthesis of Skew-Based Clock Distribution Networks. VLSI Design 7(1): 31-57 (1998) - Rajendran Panda, Farid N. Najm:
Post-Mapping Transformations for Low-Power Synthesis. VLSI Design 7(3): 289-301 (1998) - C. P. Ravikumar, Hemant Joshi:
SCOAP-based Testability Analysis from Hierarchical Netlists. VLSI Design 7(2): 131-141 (1998) - C. P. Ravikumar, Nikhil Sharma:
Testability-Driven Layout of Combinational Circuits. VLSI Design 7(4): 347-352 (1998) - Gerald Spiegel, Albrecht P. Stroele:
Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults. VLSI Design 7(2): 163-176 (1998) - Gustavo E. Téllez, Majid Sarrafzadeh:
On Rectilinear Distance-Preserving Trees. VLSI Design 7(1): 15-30 (1998) - Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
:
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. VLSI Design 7(1): 73-84 (1998) - Vivek Tiwari, Mike Tien-Chien Lee:
Power Analysis of a 32-bit Embedded Microcontroller. VLSI Design 7(3): 225-242 (1998)