![](https://dblp1.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp1.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp1.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp1.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp1.uni-trier.de/img/search.dark.16x16.png)
default search action
"Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in ..."
Sara Choi et al. (2016)
- Sara Choi, Taehui Na
, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2851-2860 (2016)
![](https://dblp1.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.