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"A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC ..."

Mohammad H. Naderi et al. (2019)

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DOI: 10.1109/TCSI.2019.2927383

access: closed

type: Journal Article

metadata version: 2020-05-22

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Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez:
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3352-3364 (2019)

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