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"Memory array architecture and decoding scheme for 3 V only sector erasable ..."

Shin'ichi Kobayashi et al. (1994)

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DOI: 10.1109/4.280695

access: closed

type: Journal Article

metadata version: 2023-05-04

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  - https://dblp.org/rec/journals/jssc/KobayashiNKNMTOAHMY94
Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara:
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. IEEE J. Solid State Circuits 29(4): 454-460 (1994)

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