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Hiroshi Onoda
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2020 – today
- 2022
- [j4]Tianhao Cheng, Hao Hu, Hitoshi Kobayashi, Hiroshi Onoda:
Visual Identification-Based Spark Recognition System. Int. J. Autom. Technol. 16(6): 766-772 (2022) - [c3]Andante Hadi Pandyaswargo
, Meilinda Fitriani Nur Maghfiroh
, Hiroshi Onoda
:
Readiness Status of Artificial Intelligence Applications on Electric Vehicles: A mini global review and analysis using the J-TRA method. ICONETSI 2022: 26:1-26:5 - 2020
- [j3]Akihisa Ogawa, Andante Hadi Pandyaswargo, Daiki Yoshidome, Hiroshi Onoda
:
Environmental and Economic Evaluation of a Mechanical Biological Treatment System for a Small and Medium-Sized Waste Treatment Facility Considering the Karatsu Smart Disaster-Resilience Base Construction Project. Int. J. Autom. Technol. 14(6): 984-998 (2020)
2010 – 2019
- 2013
- [j2]Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu:
0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration. IEEE J. Solid State Circuits 48(8): 1933-1942 (2013) - 2012
- [c2]Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu:
A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration. CICC 2012: 1-4 - 2011
- [c1]Yasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu:
0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. A-SSCC 2011: 21-24
1990 – 1999
- 1994
- [j1]Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara:
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory. IEEE J. Solid State Circuits 29(4): 454-460 (1994)
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