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"A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm ..."

Bob Verbruggen et al. (2010)

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DOI: 10.1109/ISSCC.2010.5433925

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-30

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Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC 2010: 296-297

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