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"25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling ..."

Teerachot Siriburanon et al. (2015)

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DOI: 10.1109/ISSCC.2015.7063115

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-09

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  - conf/isscc/SiriburanonKKUK15
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Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC 2015: 1-3

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