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"A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G ..."

Ashish Nayak et al. (2022)

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DOI: 10.1109/ISSCC42614.2022.9731604

access: closed

type: Conference or Workshop Paper

metadata version: 2022-03-21

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  dblp key:
  - conf/isscc/NayakCMLCRGMJCW22
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  - https://dblp.org/rec/conf/isscc/NayakCMLCRGMJCW22
Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang:
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. ISSCC 2022: 50-52

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