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"A dual-loop injection-locked PLL with all-digital background calibration ..."

Wei Deng et al. (2014)

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DOI: 10.1109/ASPDAC.2014.6742854

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-09

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Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC 2014: 21-22

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