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S. Wayne Bollinger
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1990 – 1999
- 1996
- [j3]John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang:
Design planning for high-performance ASICs. IBM J. Res. Dev. 40(4): 431-452 (1996) - 1994
- [j2]S. Wayne Bollinger, Scott F. Midkiff:
Test generation for IDDQ testing of bridging faults in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(11): 1413-1418 (1994) - 1993
- [c5]Scott F. Midkiff, S. Wayne Bollinger:
Classification of bridging faults in CMOS circuits: experimental results and implications for test. VTS 1993: 112-115 - 1992
- [c4]S. Wayne Bollinger, Scott F. Midkiff:
An investigation of circuit partitioning for parallel test generation. VTS 1992: 119-124 - 1991
- [j1]S. Wayne Bollinger, Scott F. Midkiff:
Heuristic Technique for Processor and Link Assignment in Multicomputers. IEEE Trans. Computers 40(3): 325-333 (1991) - [c3]S. Wayne Bollinger, Scott F. Midkiff:
On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits. ITC 1991: 598-607 - [c2]Scott F. Midkiff, S. Wayne Bollinger:
Circuit-level classification and testability analysis for CMOS faults. VTS 1991: 193-198
1980 – 1989
- 1988
- [c1]S. Wayne Bollinger, Scott F. Midkiff:
Processor and Link Assignment in Multicomputers Using Simulated Annealing. ICPP (1) 1988: 1-7
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