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"Design planning for high-performance ASICs."

John Y. Sayah et al. (1996)

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DOI: 10.1147/RD.404.0431

access: closed

type: Journal Article

metadata version: 2021-05-26

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  dblp key:
  - journals/ibmrd/SayahGSHABCDHHHKRTVY96
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  - https://dblp.org/rec/journals/ibmrd/SayahGSHABCDHHHKRTVY96
John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang:
Design planning for high-performance ASICs. IBM J. Res. Dev. 40(4): 431-452 (1996)

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