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ORCIDJohannes Zeppenfeld
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2010 – 2019
- 2012
[c13]Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf:
A low-overhead monitoring ring interconnect for MPSoC parameter optimization. DDECS 2012: 46-49- 2011
- [c12]Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf:
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. DDECS 2011: 225-230 - [c11]Johannes Zeppenfeld, Andreas Herkersdorf:
Applying autonomic principles for workload management in multi-core systems on chip. ICAC 2011: 3-10 - [p4]Andreas Bernauer, Johannes Zeppenfeld, Oliver Bringmann, Andreas Herkersdorf, Wolfgang Rosenstiel:
Combining Software and Hardware LCS for Lightweight On-chip Learning. Organic Computing 2011: 253-265 - [p3]Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf:
Autonomic System on Chip Platform. Organic Computing 2011: 413-425 - [p2]Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf:
Applying ASoC to Multi-core Applications for Workload Management. Organic Computing 2011: 461-472 - [p1]Andreas Herkersdorf, Andreas Lankes, Michael Meitinger, Rainer Ohlendorf, Stefan Wallentowitz, Thomas Wild, Johannes Zeppenfeld:
Hardware Support for Efficient Resource Utilization in Manycore Processor Systems. Multiprocessor System-on-Chip 2011: 57-87 - 2010
- [c10]Johannes Zeppenfeld, Andreas Herkersdorf:
Autonomic Workload Management for Multi-core Processor Systems. ARCS 2010: 49-60 - [c9]Matthias May, Norbert Wehn
, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich:
A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE 2010: 375-380 - [c8]Andreas Bernauer, Johannes Zeppenfeld, Oliver Bringmann, Andreas Herkersdorf, Wolfgang Rosenstiel:
Combining Software and Hardware LCS for Lightweight On-Chip Learning. DIPES/BICC 2010: 278-289 - [c7]Johannes Zeppenfeld, Abdelmajid Bouajila, Andreas Herkersdorf, Walter Stechele:
Towards Scalability and Reliability of Autonomic Systems on Chip. ISORC Workshops 2010: 73-80
2000 – 2009
- 2008
- [c6]Andreas Lankes, Thomas Wild, Johannes Zeppenfeld:
System Level Simulation of Autonomic SoCs with TAPES. ARCS 2008: 9-22 - [c5]Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf:
Learning Classifier Tables for Autonomic Systems on Chip. GI Jahrestagung (2) 2008: 771-778 - 2007
- [c4]Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele:
Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. DATE 2007: 498-503 - [c3]Andreas Lankes, Thomas Wild, Johannes Zeppenfeld:
Power Estimation of Time Variant SoCs with TAPES. DSD 2007: 261-264 - [c2]Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele:
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. IPDPS 2007: 1-7 - 2006
- [c1]Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel:
Organic Computing at the System on Chip Level. VLSI-SoC 2006: 338-341
Coauthor Index
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