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2020 – today
- 2023
[j19]Thomas Romera, Andrea Petreto, Florian Lemaitre, Manuel Bouyer, Quentin L. Meunier, Lionel Lacassagne, Daniel Etiemble:
Optical flow algorithms optimized for speed, energy and accuracy on embedded GPUs. J. Real Time Image Process. 20(2): 32 (2023)- 2022
- [i13]Daniel Etiemble:
Technologies and Computing Paradigms: Beyond Moore's law? CoRR abs/2206.03201 (2022) - [i12]Daniel Etiemble:
CNTFET quaternary multipliers are less efficient than the corresponding binary ones. CoRR abs/2206.03252 (2022) - [i11]Daniel Etiemble:
Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders. CoRR abs/2207.01401 (2022) - [i10]Daniel Etiemble:
Ternary and Quaternary CNTFET Full Adders are less efficient than the Binary Ones for Carry-Propagate Adders. CoRR abs/2207.04839 (2022) - 2021
- [i9]Daniel Etiemble:
Best CNTFET Ternary Adders? CoRR abs/2101.01516 (2021) - 2020
- [j18]Daniel Etiemble
:
Comments on "High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits". IEEE Access 8: 220015-220016 (2020) - [i8]Daniel Etiemble:
Best implementations of quaternary adders. CoRR abs/2005.02206 (2020) - [i7]Daniel Etiemble:
Comparing quaternary and binary multipliers. CoRR abs/2005.02678 (2020) - [i6]Daniel Etiemble:
Multivalued circuits and Interconnect issues. CoRR abs/2012.01267 (2020)
2010 – 2019
- 2019
- [i5]Daniel Etiemble:
Evolution of Technologies and Multivalued Circuits. CoRR abs/1907.01451 (2019) - [i4]Daniel Etiemble:
Coprocessors: failures and successes. CoRR abs/1907.06948 (2019) - [i3]Daniel Etiemble:
Ternary circuits: why R=3 is not the Optimal Radix for Computation. CoRR abs/1908.06841 (2019) - [i2]Daniel Etiemble:
Comparing ternary and binary adders and multipliers. CoRR abs/1908.07299 (2019) - 2018
- [j17]Laurent Cabaret, Lionel Lacassagne, Daniel Etiemble:
Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors. J. Real Time Image Process. 15(1): 173-196 (2018) - [i1]Daniel Etiemble:
45-year CPU evolution: one law and two equations. CoRR abs/1803.00254 (2018) - 2017
- [c43]Laurent Cabaret, Lionel Lacassagne, Daniel Etiemble:
Distanceless label propagation: An efficient direct connected component labeling algorithm for GPUs. IPTA 2017: 1-6 - 2016
- [j16]Antoine Tran Tan, Joel Falcou, Daniel Etiemble, Hartmut Kaiser:
Automatic Task-Based Code Generation for High Performance Domain Specific Embedded Language. Int. J. Parallel Program. 44(3): 449-465 (2016) - [c42]Lionel Lacassagne, Laurent Cabaret, Daniel Etiemble, Farouk Hebache, Andrea Petreto:
A new SIMD iterative connected component labeling algorithm. WPMVP@PPoPP 2016: 1:1-1:8 - 2015
- [j15]Florence Laguzet, Andrés Romero Mier y Terán, Michèle Gouiffès, Lionel Lacassagne, Daniel Etiemble:
Color tracking with contextual switching: real-time implementation on CPU. J. Real Time Image Process. 10(2): 403-422 (2015) - [c41]Laurent Cabaret, Lionel Lacassagne, Daniel Etiemble:
Parallel light speed labeling: An efficient connected component labeling algorithm for multi-core processors. ICIP 2015: 3486-3489 - 2014
- [c40]Lionel Lacassagne, Daniel Etiemble, Ali Hassan Zahraee, Alain Dominguez, Pascal Vezolle:
High level transforms for SIMD and low-level computer vision algorithms. WPMVP@PPoPP 2014: 49-56 - 2013
- [j14]Khaled Hamidouche, Fernando Machado Mendonca, Joel Falcou, Alba Cristina Magalhaes Alves de Melo, Daniel Etiemble:
Parallel Smith-Waterman Comparison on Multicore and Manycore Computing Platforms with BSP++. Int. J. Parallel Program. 41(1): 111-136 (2013) - [c39]H. Ye, Lionel Lacassagne, Joël Falcou, Daniel Etiemble, Laurent Cabaret, Olivier Florent:
High level tranforms toreduce energy consumption of signal and image processing operators. PATMOS 2013: 247-254 - 2012
- [c38]H. Ye, Lionel Lacassagne, Daniel Etiemble, Laurent Cabaret, Joel Falcou, Andrés Romero Mier y Terán, Olivier Florent:
Impact of high level transforms on high level synthesis for motion detection algorithm. DASIP 2012: 1-8 - 2011
- [c37]Charly Bechara, Nicolas Ventroux, Daniel Etiemble:
Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems. DSD 2011: 181-187 - [c36]Charly Bechara, Nicolas Ventroux, Daniel Etiemble:
AHDAM: An Asymmetric Homogeneous with Dynamic Allocator Manycore Chip. Facing the Multicore-Challenge 2011: 48-59 - [c35]Charly Bechara, Aurelien Berhault, Nicolas Ventroux, Stéphane Chevobbe, Yves Lhuillier, Raphaël David, Daniel Etiemble:
A small footprint interleaved multithreaded processor for embedded systems. ICECS 2011: 685-690 - [c34]Florence Laguzet, Michèle Gouiffès, Lionel Lacassagne, Daniel Etiemble:
Automatic color space switching for robust tracking. ICSIPA 2011: 295-300 - [c33]Khaled Hamidouche, Fernando Machado Mendonca, Joël Falcou, Daniel Etiemble:
Parallel Biological Sequence Comparison on Heterogeneous High Performance Computing Platforms with BSP++. SBAC-PAD 2011: 136-143 - [c32]Khaled Hamidouche, Joel Falcou, Daniel Etiemble:
A framework for an automatic hybrid MPI+OpenMP code generation. SpringSim (HPC) 2011: 48-55 - [c31]Weisheng Zhao, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert:
High Performance SoC Design Using Magnetic Logic and Memory. VLSI-SoC (Selected Papers) 2011: 10-33 - [c30]Weisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli:
Embedded MRAM for high-speed computing. VLSI-SoC 2011: 37-42 - 2010
- [c29]Charly Bechara, Nicolas Ventroux, Daniel Etiemble:
Towards a parameterizable cycle-accurate ISS in ArchC. AICCSA 2010: 1-7
2000 – 2009
- 2009
- [c28]Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel Lacassagne, Daniel Etiemble:
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor. PACT 2009: 67-76 - 2005
- [j13]Daniel Etiemble, Lionel Lacassagne:
Des flottants 16 bits sur microprocesseurs d'usage général pour images et multimédia. Tech. Sci. Informatiques 24(6): 645-665 (2005) - [c27]Lionel Lacassagne, Daniel Etiemble, S. A. Ould Kablia:
16-bit Floating Point Instructions for Embedded Multimedia Applications. CAMP 2005: 198-203 - [c26]Daniel Etiemble, Samir Bouaziz, Lionel Lacassagne:
Customizing 16-bit FP Instructions on a NIOS II Processor for FPGA Image and Media Processing. ESTIMedia 2005: 61-66 - 2004
- [c25]Daniel Etiemble, Lionel Lacassagne:
16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing. ICPP 2004: 540-547 - 2003
- [j12]Daniel Etiemble:
Why M-Valued Circuits are Restricted to a Small Niche. J. Multiple Valued Log. Soft Comput. 9(1): 109-123 (2003) - 2002
- [j11]Daniel Etiemble:
Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware". Theor. Comput. Sci. 279(1-2): 3-27 (2002) - [j10]Franck Cappello, Daniel Etiemble:
MPI ou MPI+OpenMP sur grappes de multiprocesseurs? Tech. Sci. Informatiques 21(2): 253-272 (2002) - [c24]Daniel Etiemble:
Numerical Applications and Sub-Word Parallelism: The NAS Benchmarks on a Pentium 4. HPCS 2002: 205-212 - [c23]Daniel Etiemble:
Optimizing DSP and media benchmarks for Pentium 4: hardware and software issues. ICME (2) 2002: 109-112 - 2001
- [j9]Franck Cappello, Olivier Richard, Daniel Etiemble:
Understanding performance of SMP clusters running MPI programs. Future Gener. Comput. Syst. 17(6): 711-720 (2001) - 2000
- [c22]Franck Cappello, Olivier Richard, Daniel Etiemble:
Investigating the Performance of Two Programming Models for Clusters of SMP PCs. HPCA 2000: 349-359 - [c21]Franck Cappello, Daniel Etiemble:
MPI versus MPI+OpenMP on IBM SP for the NAS Benchmarks. SC 2000: 12
1990 – 1999
- 1999
- [c20]Franck Cappello, Olivier Richard, Daniel Etiemble:
Performance of the NAS Benchmarks on a Cluster of SMP PCs Using a Parallelization of the MPI Programs with OpenMP. PaCT 1999: 339-350 - [c19]Franck Cappello, Olivier Richard, Daniel Etiemble:
Performance Evaluation of Two Programming Models for a Cluster of PC Biprocessors. PDPTA 1999: 1912-1918 - 1997
- [c18]P. Bosch, A. Carloganu, Daniel Etiemble:
Complete x86 instruction trace generation from hardware bus collect. EUROMICRO 1997: 402-408 - [c17]A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble:
Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces. EUROMICRO 1997: 409- - [c16]Cécile Germain, Jacques Laminie, Marie Pallud, Daniel Etiemble:
An HPF Case Study of a Domain-Decomposition Based Irregular Application. PaCT 1997: 201-209 - [c15]Franck Cappello, Daniel Etiemble:
Communications in Parallel Architectures and Networks of Workstations: From Standardisation to New Standards. PaCT 1997: 298-310 - 1995
- [c14]Keivan Navi, Daniel Etiemble:
From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. ISMVL 1995: 58-63 - [c13]Daniel Etiemble, Cécile Germain:
Standard Microprocessors Versus Custom Processing Elements for Massively Parallel Architectures. PaCT 1995: 320-325 - 1994
- [j8]Daniel Etiemble, Jean-Claude Syre:
Parallel architecture and language in Europe. Future Gener. Comput. Syst. 10(1): 1-2 (1994) - [c12]A. Kazeminejad, Keivan Navi, Daniel Etiemble:
CML Current Mode Full Adders for 2.5-V Power Supply. ISMVL 1994: 10-14 - [c11]Keivan Navi, A. Kazeminejad, Daniel Etiemble:
Performance of CMOS Current Mode Full Adders. ISMVL 1994: 27-34 - 1993
- [j7]Cécile Germain, Jean-Luc Béchennec, Daniel Etiemble, Jean-Paul Sansonnet:
A Communication Architecture for a Massively Parallel Message-Passing Multicomputer. J. Parallel Distributed Comput. 19(4): 338-348 (1993) - [j6]Vincent Néri, Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble:
Hardware features of the static communication network of a parallel architecture. Microprocess. Microprogramming 38(1-5): 19-24 (1993) - [c10]Daniel Etiemble, Keivan Navi:
Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system. IEEE Symposium on Computer Arithmetic 1993: 194-201 - [c9]Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble:
Balanced Distributed Memory Parallel Computers. ICPP (1) 1993: 72-76 - [c8]Daniel Etiemble, Keivan Navi:
A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems. ISMVL 1993: 216-221 - [c7]Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Damien Gautier de Lahaut, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble:
A Parralel Architecture Based on Compiled Communication Schemes. PARCO 1993: 371-378 - 1992
- [c6]Daniel Etiemble:
On the Performance of Multivalued Integrated Circuits: Past, Present and Future. ISMVL 1992: 156-164 - [e1]Daniel Etiemble, Jean-Claude Syre:
PARLE '92: Parallel Architectures and Languages Europe, 4th International PARLE Conference, Paris, France, June 15-18, 1992, Proceedings. Lecture Notes in Computer Science 605, Springer 1992, ISBN 3-540-55599-4 [contents] - 1991
- [j5]Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble:
3D hardware packages for parallel architectures. Microprocessing and Microprogramming 32(1-5): 171-177 (1991) - 1990
- [j4]Franck Cappello, Jean-Luc Béchennec, Daniel Etiemble:
A risc central processing unit for a massivelly parallel architecture. Microprocessing and Microprogramming 30(1-5): 33-39 (1990) - [c5]Daniel Etiemble, Christophe Chanussot, Vincent Néri:
4-Valued BiCMOS Circuits for the Transmission System of a Massively Parallel Architecture. ISMVL 1990: 348-354
1980 – 1989
- 1988
- [j3]Daniel Etiemble, Michel Israël:
Comparison of Binary and Multivalued ICs According to VLSI Criteria. Computer 21(4): 28-42 (1988) - [c4]Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec:
A highly parallel processor with an instruction set including relational algebra. ICCD 1988: 537-538 - 1987
- [c3]Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec, He Hé:
The Database Processor 'RAPID'. IWDM 1987: 171-187 - 1984
- [c2]Daniel Etiemble, V. Adeline, Nguyen H. Duyet, J. C. Ballegeer:
Micro-computer oriented algorithms for delay evaluation of MOS gates. DAC 1984: 358-364 - 1980
- [j2]Daniel Etiemble:
Multivalued I2L Circuits for TSC Checkers. IEEE Trans. Computers 29(6): 537-540 (1980)
1970 – 1979
- 1978
- [c1]Daniel Etiemble:
TTL circuits for a 4-valued bus a way to reduce package and interconnections. MVL 1978: 7-13 - 1977
- [j1]Daniel Etiemble, Michel Israël:
Implementation of Ternary Circuits with Binary Integrated Circuits. IEEE Trans. Computers 26(12): 1222-1233 (1977)
Coauthor Index
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last updated on 2024-06-19 21:50 CEST by the dblp team
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