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2010 – 2019
- 2014
[j2]Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun:
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 559-563 (2014)- 2012
- [c5]Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, Kuo-Hsing Cheng:
A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology. ISCAS 2012: 2597-2600 - 2011
- [j1]Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang:
A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique. IEEE J. Solid State Circuits 46(5): 1198-1213 (2011) - [c4]Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang:
A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation. ESSCIRC 2011: 447-450 - 2010
- [c3]Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng:
A 3 GHz DLL-based clock generator with stuck locking protection. ICECS 2010: 106-109
2000 – 2009
- 2008
- [c2]Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw:
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS 2008: 64-67 - 2007
- [c1]Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su:
A Sub-1V Low-Power High-Speed Static Frequency Divider. ISCAS 2007: 3848-3851
Coauthor Index
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