default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDYongliang Zhou
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[j17]Shan Shen
, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu:
Ultra8T: A sub-threshold 8T SRAM with leakage detection. Integr. 98: 102233 (2024)- [j16]Yue Zhao, Yunlong Liu, Jian Zheng, Zhongzhen Tong, Xin Wang, Runru Yu, Xiulong Wu, Yongliang Zhou, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin:
Configurable in-memory computing architecture based on dual-port SRAM. Microelectron. J. 147: 106163 (2024) - [j15]Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng:
An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices. Microelectron. J. 151: 106308 (2024) - [j14]Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu:
A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 187-200 (2024) - [j13]Yongliang Zhou, Xiao Lin, Zixuan Zhou, Yingxue Sun, Yiming Wei, Zhen Yang, Chengxing Dai, JingXue Zhong, Xiulong Wu, Chunyu Peng:
Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4019-4031 (2024) - [j12]Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu:
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 597-608 (2024) - [j11]Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu:
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 883-896 (2024) - [c12]Yongliang Zhou, Zhen Yang, Yiming Wei, Xiao Lin, Saiai Wu, Wenjuan Lu, Chunyu Peng, Xin Li, Xiulong Wu:
A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM. ISCAS 2024: 1-5 - 2023
- [j10]Shan Shen, Hao Xu, Yongliang Zhou, Wenjian Yu:
A Single-Ended Offset-Canceling Sense Amplifier Enabling Wide-Voltage Operations. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1139-1143 (2023) - [c11]An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang:
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. ISSCC 2023: 128-129 - [c10]Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang:
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. ISSCC 2023: 134-135 - [c9]Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan:
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. ISSCC 2023: 500-501 - [i1]Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu:
Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection. CoRR abs/2306.08936 (2023) - 2022
- [j9]Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner:
Writing-only in-MRAM computing paradigm for ultra-low power applications. Microprocess. Microsystems 90: 104449 (2022) - [c8]Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang:
A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators. APCCAS 2022: 501-504 - [c7]An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang:
ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. ISCAS 2022: 2276-2280 - [c6]Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si:
SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. ISCAS 2022: 3383-3387 - 2021
- [j8]Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang:
A survey of in-spin transfer torque MRAM computing. Sci. China Inf. Sci. 64(6) (2021) - [j7]Hao Cai, Juntong Chen, Yongliang Zhou, Weisheng Zhao:
Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2633-2639 (2021) - [c5]Xin Si, Yongliang Zhou, Jun Yang, Meng-Fan Chang:
Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices. ASICON 2021: 1-4 - [c4]Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang:
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. ISOCC 2021: 195-196 - [c3]Yufei Wang, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xin Si:
Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices. UCET 2021: 47-52 - 2020
- [j6]Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu:
Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing. CCF Trans. High Perform. Comput. 2(3): 282-296 (2020) - [j5]Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Yongliang Zhou, Hao Cai:
Magnetic Tunnel Junction Applications. Sensors 20(1): 121 (2020) - [j4]Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang:
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1602-1614 (2020) - [j3]Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang:
MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. IEEE Trans. Circuits Syst. 67-II(12): 3352-3356 (2020)
2010 – 2019
- 2019
- [c2]Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang:
A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. NANOARCH 2019: 1-6 - 2016
- [j2]Zhengping Li, Mingming Xie, Xincun Ji, Yongliang Zhou:
Robust activating timing for SRAM SA with replica cell voltage boosted circuit. IEICE Electron. Express 13(10): 20160302 (2016) - 2011
- [j1]Hongwei Liu, Yongliang Zhou:
Rank-two residue iteration method for nonnegative matrix factorization. Neurocomputing 74(17): 3305-3312 (2011) - 2010
- [c1]Na Wei, Yongliang Zhou:
Analysis of how to use the GEB developing. ICEE 2010: 3723-3725
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-09-22 00:36 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
