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Yung-Chung Lo
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2010 – 2019
- 2015
- [c2]Yung-Chung Lo, Negar Rashidi, Yin-Huan Hwang, José Silva-Martínez:
A 0.6ps jitter 2-16 GHz 130nm CMOS frequency synthesizer for broadband applications. ISCAS 2015: 3048-3051 - 2013
- [j4]Hyung-Joon Jeon, Raghavendra Kulkarni, Yung-Chung Lo, Jusung Kim, José Silva-Martínez:
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy. IEEE J. Solid State Circuits 48(6): 1398-1415 (2013) - 2012
- [j3]Ahmed A. Helmy, Hyung-Joon Jeon, Yung-Chung Lo, Andreas J. Larsson, Raghavendra Kulkarni, Jusung Kim, José Silva-Martínez, Kamran Entesari:
A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer. IEEE J. Solid State Circuits 47(10): 2467-2483 (2012) - [j2]Haitao Tong, Shanfeng Cheng, Yung-Chung Lo, Aydin I. Karsilayan
, José Silva-Martínez:
An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1871-1879 (2012) - 2010
- [j1]Cho-Ying Lu, Marvin Onabajo, Venkata Gadde, Yung-Chung Lo, Hsien-Pu Chen, Vijayaramalingam Periasamy, José Silva-Martínez:
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback. IEEE J. Solid State Circuits 45(9): 1795-1808 (2010)
2000 – 2009
- 2009
- [c1]Yung-Chung Lo, Hsien-Pu Chen, José Silva-Martínez, Sebastian Hoyos:
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider. CICC 2009: 259-262
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