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ORCIDRakesh Malik
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2010 – 2019
- 2018
[j3]Jai Narayan Tripathi
, Ramachandra Achar, Rakesh Malik:
Fast Analysis of Time Interval Error in Current-Mode Drivers. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 367-377 (2018)- 2017
- [j2]Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065-mm2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB. IEEE J. Solid State Circuits 52(7): 1927-1939 (2017) - [c15]Hitesh Shrimali, Vijender Kumar Sharma, Jai Narayan Tripathi, Rakesh Malik:
Nonlinear modeling and analysis of buck converter using volterra series. ICECS 2017: 222-226 - [c14]Vijender Kumar Sharma, Hitesh Shrimali, Jai Narayan Tripathi, Rakesh Malik:
Distortion analysis for a DC-DC buck converter. ISOCC 2017: 212-213 - 2016
- [c13]Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB. ESSCIRC 2016: 165-168 - 2015
- [c12]Jai Narayan Tripathi, Hiten Advani, Raj Kumar Nagpal, Vijender Kumar Sharma, Rakesh Malik:
Analysis of a serial link for power supply induced jitter. SoCC 2015: 127-130 - 2014
- [c11]Jai Narayan Tripathi, Ashutosh Mahajan, Jayanta Mukherjee, Raj Kumar Nagpal, Rakesh Malik, Nitin Gupta:
Decoupling network optimization in high speed systems by mixed-integer programming. ISCAS 2014: 1010-1013 - 2013
- [c10]Rakesh Malik, Partha Pratim Roy, Umapada Pal, Fumitaka Kimura:
Handwritten Musical Document Retrieval Using Music-Score Spotting. ICDAR 2013: 832-836 - [c9]Jai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee, Prakash R. Apte:
Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization. ISQED 2013: 670-675 - 2012
- [j1]Rakesh Malik:
Selling to the BRIC: the background to the scholarly publishing market in India. Learn. Publ. 25(3): 213-218 (2012) - [c8]Jai Narayan Tripathi, Nitin Kumar Chhabra, Raj Kumar Nagpal, Rakesh Malik, Jayanta Mukherjee:
Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms. ISCAS 2012: 361-364 - [c7]Jai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee:
Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization. ISQED 2012: 525-528 - 2011
- [c6]Raj Kumar Nagpal, Jai Narayan Tripathi, Rakesh Malik:
Cost-effective optimization of serial link system for Signal Integrity and Power Integrity. ISQED 2011: 548-552 - 2010
- [c5]Abhishek Pathak, Sushanta K. Mandal, Raj Kumar Nagpal, Rakesh Malik:
Modelling of Power Distribution Network and Decoupling Network Design for High Speed VLSI Design. DELTA 2010: 194- - [c4]Jai Narayan Tripathi, Raj Kumar Nagpal, Rakesh Malik:
Robust optimization of serial link system for signal integrity and power integrity. NESEA 2010: 1-8
2000 – 2009
- 2009
- [c3]Raj Kumar Nagpal, Rakesh Malik, Jai Narayan Tripathi:
Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links. DSD 2009: 742-745 - 2008
- [c2]Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. CICC 2008: 305-308 - 2007
- [c1]Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process. CICC 2007: 189-192
Coauthor Index
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