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ORCIDLounis Kessal
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2020 – today
- 2023
[j8]Tarek Elouaret
, Sylvain Colomer, Frédéric de Melo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman:
Implementation of a Bio-Inspired Neural Architecture for Autonomous Vehicles on a Multi-FPGA Platform. Sensors 23(10): 4631 (2023)- 2022
- [c16]Tarek Elouaret, Sylvain Colomer, Frédéric Demelo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman:
Implementation of a bio-inspired neural architecture for autonomous vehicle on a reconfigurable platform. ISIE 2022: 661-666
2010 – 2019
- 2019
- [j7]Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Emmanuel Boutillon, Chris Winstead, Bane Vasic:
A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 403-416 (2019) - [c15]Tarek Elouaret, Stéphane Zuckerman, Lounis Kessal, Yoan Espada, Nicolas Cuperlier, Guillaume Bresson, Fethi Ben Ouezdou, Olivier Romain:
Position Paper: Prototyping Autonomous Vehicles Applications with Heterogeneous Multi-FpgaSystems. UCET 2019: 1-2 - 2018
- [j6]Khoa Le, David Declercq, Fakhreddine Ghaffari, Lounis Kessal, Oana Boncalo, Valentin Savin:
Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2183-2195 (2018) - [c14]Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo:
Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. ISCAS 2018: 1-5 - 2017
- [c13]Franklin Cochachin, David Declercq, Emmanuel Boutillon, Lounis Kessal:
Density evolution thresholds for noise-against-noise min-sum decoders. PIMRC 2017: 1-7 - 2014
- [c12]Lotfi Bendaouia, Hassen Salhi, Si Mahmoud Karabernou, Lounis Kessal, Fayçal Ykhlef:
FPGA-implementation of a bio-inspired medical hearing aid based DWT-OLA. ICAILP 2014: 806-811 - 2012
- [j5]Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Lounis Kessal, Fabrice Lemonnier, Jimmy Le Rhun:
Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications. ACM Trans. Reconfigurable Technol. Syst. 5(3): 14:1-14:16 (2012) - 2011
- [c11]Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal:
Dataflow programming model for reconfigurable computing. ReCoSoC 2011: 1-8
2000 – 2009
- 2009
- [j4]Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal:
Hardware Architecture for Pattern Recognition in Gamma-Ray Experiment. EURASIP J. Embed. Syst. 2009 (2009) - 2008
- [j3]Lounis Kessal, Nicolas Abel, Si Mahmoud Karabernou, Didier Demigny:
Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing. J. Real Time Image Process. 3(3): 131-147 (2008) - [c10]Narayanan Ramanan, Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal:
Neural network hardware architecture for pattern recognition in the HESS2 project. ESANN 2008: 343-348 - 2007
- [j2]Si Mahmoud Karabernou, Lounis Kessal, Fayçal Terranti:
Erratum to "Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm" [Image and Vision Computing 23 (2005) 1009-1017]. Image Vis. Comput. 25(6): 1032 (2007) - 2006
- [c9]Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny:
Clear Stream towards Dynamically Reconfigurable Systems on Chip. ReCoSoC 2006: 98-104 - 2004
- [c8]Nicolas Abel, Lounis Kessal, Didier Demigny:
Design flexibility using fpga dynamical reconfiguration. ICIP 2004: 2821-2824 - 2003
- [j1]Lounis Kessal, Nicolas Abel, Didier Demigny:
Real-time image processing with dynamically reconfigurable architecture. Real Time Imaging 9(5): 297-313 (2003) - 2001
- [c7]P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, Si Mahmoud Karabernou:
Two ASIC for Low and Middle Levels of Real Time Image Processing. VLSI-SOC 2001: 3-14 - [c6]Didier Demigny, Lounis Kessal, J. Pons:
Fast Recursive Implementation of the Gaussian Filter. VLSI-SOC 2001: 39-49 - [c5]Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, Si Mahmoud Karabernou:
Reconfigurable Architecture Using High Speed FPGA. VLSI-SOC 2001: 75-86 - 2000
- [c4]Didier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani:
How to Use High Speed Reconfigurable FPGA for Real Time Image Processing? CAMP 2000: 240- - [c3]Lounis Kessal, Didier Demigny, N. Boudouani, R. Bourguiba:
Reconfigurable Hardware for Real Time Image Processing. ICIP 2000: 110-113
1990 – 1999
- 1997
- [c2]F. G. Lorca, Lounis Kessal, Didier Demigny:
Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. ICIP (2) 1997: 406-409 - 1995
- [c1]Didier Demigny, F. G. Lorca, Lounis Kessal:
Evaluation of edge detectors performances with a discrete expression of Canny's criteria. ICIP 1995: 169-172
Coauthor Index
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