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2010 – 2019
- 2012
[c2]Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS 2012: 1831-1834- 2011
- [c1]Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC 2011: 197-200
2000 – 2009
- 2006
- [j4]Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh:
An AND-type match-line scheme for high-performance energy-efficient content addressable memories. IEEE J. Solid State Circuits 41(5): 1108-1119 (2006) - 2005
- [j3]Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen:
Design techniques for single-low-VDD CMOS systems. IEEE J. Solid State Circuits 40(5): 1157-1165 (2005) - 2003
- [j2]Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang:
Energy Efficient Caching-on-Cache Architectures for Embedded Systems. J. Inf. Sci. Eng. 19(5): 809-825 (2003) - 2000
- [j1]Jinn-Shyan Wang, Wayne Tseng, Hung-Yu Li:
Low-power embedded SRAM with the current-mode write technique. IEEE J. Solid State Circuits 35(1): 119-124 (2000)
Coauthor Index
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