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ORCIDAdel Dokhanchi
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2010 – 2019
- 2019
[c12]Anand Balakrishnan
, Aniruddh Gopinath Puranic, Xin Qin, Adel Dokhanchi, Jyotirmoy V. Deshmukh, Heni Ben Amor, Georgios Fainekos:
Specifying and Evaluating Quality Metrics for Vision-based Perception Systems. DATE 2019: 1433-1438- [c11]Mohammad Hekmatnejad, Shakiba Yaghoubi, Adel Dokhanchi, Heni Ben Amor, Aviral Shrivastava, Lina J. Karam, Georgios Fainekos:
Encoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic. MEMOCODE 2019: 6:1-6:11 - 2018
- [j3]Bardh Hoxha, Adel Dokhanchi, Georgios Fainekos:
Mining parametric temporal logic properties in model-based design for cyber-physical systems. Int. J. Softw. Tools Technol. Transf. 20(1): 79-93 (2018) - [j2]Adel Dokhanchi, Bardh Hoxha, Georgios Fainekos:
Formal Requirement Debugging for Testing and Verification of Cyber-Physical Systems. ACM Trans. Embed. Comput. Syst. 17(2): 34:1-34:26 (2018) - [c10]Adel Dokhanchi, Shakiba Yaghoubi, Bardh Hoxha, Georgios Fainekos, Gidon Ernst, Zhenya Zhang, Paolo Arcaini, Ichiro Hasuo, Sean Sedwards:
ARCH-COMP18 Category Report: Results on the Falsification Benchmarks. ARCH@ADHS 2018: 104-109 - [c9]Adel Dokhanchi, Heni Ben Amor, Jyotirmoy V. Deshmukh, Georgios Fainekos:
Evaluating Perception Systems for Autonomous Vehicles Using Quality Temporal Logic. RV 2018: 409-416 - 2017
- [b1]Adel Dokhanchi:
From Formal Requirement Analysis to Testing and Monitoring of Cyber-Physical Systems. Arizona State University, Tempe, USA, 2017 - [c8]Adel Dokhanchi, Shakiba Yaghoubi, Bardh Hoxha, Georgios Fainekos:
Vacuity aware falsification for MTL request-response specifications. CASE 2017: 1332-1337 - [c7]Adel Dokhanchi, Shakiba Yaghoubi, Bardh Hoxha, Georgios Fainekos:
ARCH-COMP17 Category Report: Preliminary Results on the Falsification Benchmarks. ARCH@CPSWeek 2017: 170-174 - 2016
- [c6]Adel Dokhanchi, Bardh Hoxha, Cumhur Erkan Tuncali, Georgios Fainekos:
An efficient algorithm for monitoring practical TPTL specifications. MEMOCODE 2016: 184-193 - [i4]Adel Dokhanchi, Bardh Hoxha, Georgios Fainekos:
Formal Requirement Elicitation and Debugging for Testing and Verification of Cyber-Physical Systems. CoRR abs/1607.02549 (2016) - [i3]Adel Dokhanchi, Bardh Hoxha, Cumhur Erkan Tuncali, Georgios Fainekos:
An Efficient Algorithm for Monitoring Practical TPTL Specifications. CoRR abs/1612.03140 (2016) - 2015
- [c5]Adel Dokhanchi, Aditya Zutshi, Rahul T. Sriniva, Sriram Sankaranarayanan, Georgios Fainekos:
Requirements driven falsification with coverage metrics. EMSOFT 2015: 31-40 - [c4]Adel Dokhanchi, Bardh Hoxha, Georgios Fainekos:
Metric interval temporal logic specification elicitation and debugging. MEMOCODE 2015: 70-79 - [i2]Bardh Hoxha, Adel Dokhanchi, Georgios Fainekos:
Querying Parametric Temporal Logic Properties in Model Based Design. CoRR abs/1512.07956 (2015) - 2014
- [c3]Adel Dokhanchi, Bardh Hoxha, Georgios Fainekos:
On-Line Monitoring for Temporal Logic Robustness. RV 2014: 231-246 - [i1]Adel Dokhanchi, Bardh Hoxha, Georgios Fainekos:
On-Line Monitoring for Temporal Logic Robustness. CoRR abs/1408.0045 (2014) - 2012
- [j1]Mohammad Taghi Teimoori, Ali Jahanian, Adel Dokhanchi:
Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects. IEICE Trans. Electron. 95-C(10): 1610-1619 (2012) - 2011
- [c2]Adel Dokhanchi, Ali Jahanian, Esfandiar Mehrshahi, Mohammad Taghi Teimoori:
Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage. ISVLSI 2011: 1-6
2000 – 2009
- 2008
- [c1]Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani:
Performance Improvement of Physical Retiming with Shortcut Insertion. ISVLSI 2008: 215-220
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