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Vishal Khandelwal
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Books and Theses
- 2007
- [b1]Vishal Khandelwal:
Variability-Aware VLSI Design Automation For Nanoscale Technologies. University of Maryland, College Park, MD, USA, 2007
Journal Articles
- 2008
- [j8]Vishal Khandelwal, Ankur Srivastava
:
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 610-620 (2008) - 2007
- [j7]Vishal Khandelwal, Ankur Srivastava
:
Active mode leakage reduction using fine-grained forward body biasing strategy. Integr. 40(4): 561-570 (2007) - [j6]Vishal Khandelwal, Ankur Srivastava
:
Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1246-1255 (2007) - [j5]Vishal Khandelwal, Ankur Srivastava
:
A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 206-215 (2007) - 2006
- [j4]Jennifer L. Wong
, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
, Miodrag Potkonjak:
A statistical methodology for wire-length prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1327-1336 (2006) - [j3]Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
:
Probabilistic Evaluation of Solutions in Variability-Driven Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 3010-3016 (2006) - 2005
- [j2]Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
:
Simultaneous Vt selection and assignment for leakage optimization. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 762-765 (2005) - 2004
- [j1]Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
:
Empirical models for net-length probability distribution and applications. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1066-1075 (2004)
Conference and Workshop Papers
- 2023
- [c21]Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, Sung Kyu Lim:
RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning. DAC 2023: 1-6 - 2022
- [c20]Vishal Khandelwal:
Machine-Learning Enabled PPA Closure for Next-Generation Designs. ISPD 2022: 49 - [c19]Yi-Chen Lu, Wei-Ting Chan, Vishal Khandelwal, Sung Kyu Lim:
Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction. MLCAD 2022: 97-102 - 2021
- [c18]Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim
:
RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. DAC 2021: 733-738 - [c17]Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim:
Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. ICCAD 2021: 1-9 - [c16]Siddhartha Nath, Vishal Khandelwal:
Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes. ISPD 2021: 83-90 - 2020
- [c15]Vishal Khandelwal:
Machine-Learning Enabled Next-Generation Physical Design - An EDA Perspective. MLCAD 2020: 135 - 2009
- [c14]Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer
:
On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD 2009: 51-58 - 2007
- [c13]Vishal Khandelwal, Ankur Srivastava
:
Monte-Carlo driven stochastic optimization framework for handling fabrication variability. ICCAD 2007: 105-110 - [c12]Jennifer L. Wong
, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
, Miodrag Potkonjak:
Statistical timing analysis using Kernel smoothing. ICCD 2007: 97-102 - [c11]Vishal Khandelwal, Ankur Srivastava
:
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. ISPD 2007: 11-18 - [c10]Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
:
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes. VLSI Design 2007: 259-264 - [c9]Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava
:
Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. VLSI Design 2007: 571-576 - 2005
- [c8]Vishal Khandelwal, Ankur Srivastava:
A general framework for accurate statistical timing analysis considering correlations. DAC 2005: 89-94 - 2004
- [c7]Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
:
High level techniques for power-grid noise immunity. ACM Great Lakes Symposium on VLSI 2004: 13-18 - [c6]Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
:
Variability inspired implementation selection problem. ICCAD 2004: 423-427 - [c5]Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava:
Efficient statistical timing analysis through error budgeting. ICCAD 2004: 473-477 - [c4]Vishal Khandelwal, Ankur Srivastava:
Leakage control through fine-grained placement and sizing of sleep transistors. ICCAD 2004: 533-536 - [c3]Jennifer L. Wong
, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava
, Miodrag Potkonjak:
Wire-length prediction using statistical techniques. ICCAD 2004: 702-705 - [c2]Vishal Khandelwal, Ankur Srivastava
:
Active mode leakage reduction using fine-grained forward body biasing strategy. ISLPED 2004: 150-155 - 2003
- [c1]Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava:
A Probabilistic Approach to Buffer Insertion. ICCAD 2003: 560-567
Reference Works
- 2008
- [r1]Vishal Khandelwal, Ankur Srivastava:
Basic Algorithmic Techniques. Handbook of Algorithms for Physical Design Automation 2008
Coauthor Index
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