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Masayuki Shimoda
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Journal Articles
- 2023
- [j5]Takafumi Tanaka
, Masayuki Shimoda
:
Pre- and post-processing techniques for reinforcement-learning-based routing and spectrum assignment in elastic optical networks. J. Opt. Commun. Netw. 15(12): 1019 (2023) - 2021
- [j4]Masayuki Shimoda
, Youki Sada, Hiroki Nakahara
:
FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. J. Signal Process. Syst. 93(5): 499-512 (2021) - 2020
- [j3]Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
:
SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. 103-D(12): 2463-2470 (2020) - 2019
- [j2]Hiroki Nakahara
, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato:
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. 102-D(5): 1003-1011 (2019) - [j1]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
:
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. 102-D(5): 1020-1028 (2019)
Conference and Workshop Papers
- 2024
- [c17]Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi:
BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem. ISCAS 2024: 1-5 - 2021
- [c16]Masayuki Shimoda, Takafumi Tanaka:
Mask RSA: End-To-End Reinforcement Learning-based Routing and Spectrum Assignment in Elastic Optical Networks. ECOC 2021: 1-4 - [c15]Takafumi Tanaka, Masayuki Shimoda:
Impact of Operational Mode Selection and Grooming Policies on Auxiliary Graph-Based Multi-layer Network Planning. ECOC 2021: 1-4 - 2020
- [c14]Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara:
Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops 2020: 143-146 - 2019
- [c13]Masayuki Shimoda, Youki Sada, Hiroki Nakahara
:
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. ARC 2019: 371-386 - [c12]Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato:
An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA 2019: 186 - [c11]Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato:
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL 2019: 180-186 - [c10]Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara:
An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. FPL 2019: 413-414 - [c9]Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara:
A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. FPT 2019: 267-270 - [c8]Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC 2019: 93-100 - [c7]Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara:
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig 2019: 1-5 - 2018
- [c6]Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato:
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL 2018: 457-458 - [c5]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL 2018: 461-462 - [c4]Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato:
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT 2018: 298-301 - [c3]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART 2018: 10:1-10:6 - 2017
- [c2]Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato:
A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. FPL 2017: 1 - [c1]Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
All binarized convolutional neural network and its implementation on an FPGA. FPT 2017: 291-294
Coauthor Index
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