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Shumpei Morita
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2020 – today
- 2022
- [j4]Shumpei Morita, Song Bian, Michihiro Shintani, Takashi Sato:
Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5515-5525 (2022)
2010 – 2019
- 2018
- [c5]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. ASP-DAC 2018: 631-636 - [c4]Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
A study on NBTI-induced delay degradation considering stress frequency dependence. ISQED 2018: 251-256 - 2017
- [j3]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1464-1472 (2017) - [j2]Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Identification and Application of Invariant Critical Paths under NBTI Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2797-2806 (2017) - [j1]Hiromitsu Awano, Shumpei Morita, Takashi Sato:
Scalable Device Array for Statistical Characterization of BTI-Related Parameters. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1455-1466 (2017) - [c3]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Comparative study of path selection and objective function in replacing NBTI mitigation logic. ISQED 2017: 426-431 - 2016
- [c2]Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. ACM Great Lakes Symposium on VLSI 2016: 203-208 - [c1]Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato:
Nonlinear delay-table approach for full-chip NBTI degradation prediction. ISQED 2016: 307-312
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