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ORCIDJinhua Cui 0001
Person information
- affiliation: Huazhong University of Science and Technology, Wuhan, China
- affiliation (Ph.D., 2018): Xi'an Jiaotong University, China
- unicode name: 崔金华
Other persons with the same name
- Jinhua Cui 0002
![[0000-0001-5716-4995]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-5716-4995")
— Hunan University, Changsha, China (and 1 more)
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2020 – today
- 2024
[j11]Debin Liu, Laurence T. Yang, Ruonan Zhao, Jinhua Cui, Xiangli Yang:
An Efficient Tensor-Based Transformer for Industrial Internet of Things. IEEE Trans. Netw. Sci. Eng. 11(3): 2574-2585 (2024)- 2023
- [j10]Jinhua Cui, Zhimin Zeng, Jianhang Huang, Weiqi Yuan, Laurence T. Yang:
Improving 3-D NAND SSD Read Performance by Parallelizing Read-Retry. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 768-780 (2023) - [j9]Weiguang Liu, Jinhua Cui, Tiantian Li, Junwei Liu, Laurence T. Yang:
A Space-Efficient Fair Cache Scheme Based on Machine Learning for NVMe SSDs. IEEE Trans. Parallel Distributed Syst. 34(1): 383-399 (2023) - [c10]Jinhua Cui, Kai Tang, Laurence T. Yang:
A Fast Secure Deletion Strategy for High-Density Flash Memory through WOM-v Codes. DAC 2023: 1-6 - 2022
- [j8]Jinhua Cui, Weiguang Liu, Jianhang Huang, Laurence T. Yang:
ADS: Leveraging Approximate Data for Efficient Data Sanitization in SSDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1771-1784 (2022) - [j7]Jinhua Cui, Cheng Liu, Junwei Liu, Jianhang Huang, Laurence T. Yang:
Exploiting Uncorrectable Data Reuse for Performance Improvement of Flash Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1785-1798 (2022) - [c9]Zhimin Zeng, Xinyu Chen, Laurence T. Yang, Jinhua Cui:
IMRSim: A Disk Simulator for Interlaced Magnetic Recording Technology. NPC 2022: 267-273 - [i1]Zhimin Zeng, Xinyu Chen, Laurence T. Yang, Jinhua Cui:
IMRSim: A Disk Simulator for Interlaced Magnetic Recording Technology. CoRR abs/2206.14368 (2022) - 2021
- [j6]Jinhua Cui, Junwei Liu, Jianhang Huang, Laurence T. Yang:
SmartHeating: On the Performance and Lifetime Improvement of Self-Healing SSDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 52-65 (2021) - 2020
- [j5]Jinhua Cui, Youtao Zhang, Liang Shi, Chun Jason Xue, Jun Yang, Weiguang Liu, Laurence T. Yang:
Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems. J. Syst. Archit. 103: 101685 (2020) - [c8]Jinhua Cui, Weiguang Liu, Jianhang Huang, Laurence T. Yang:
Exploiting Disturbance-Aware Read Redirection for Performance Improvement in 3D Flash Memory. ACM Great Lakes Symposium on VLSI 2020: 95-100 - [c7]Weiguang Liu, Jinhua Cui, Junwei Liu, Laurence T. Yang:
MLCache: A Space-Efficient Cache Scheme based on Reuse Distance and Machine Learning for NVMe SSDs. ICCAD 2020: 58:1-58:9 - [c6]Jinhua Cui, Junwei Liu, Jianhang Huang, Haoran Zhu, Laurence Tianruo Yang:
ApproxRefresh: Enabling Uncorrectable Data Reuse on Flash Memory with Approximate Read Awareness. LCTES 2020: 26-37
2010 – 2019
- 2018
- [j4]Jinhua Cui, Youtao Zhang, Weiguo Wu, Jun Yang, Yinfeng Wang, Jianhang Huang:
DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1546-1559 (2018) - [j3]Jinhua Cui, Youtao Zhang, Liang Shi, Chun Jason Xue, Weiguo Wu, Jun Yang:
ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1957-1970 (2018) - [c5]Jinhua Cui, Youtao Zhang, Jianhang Huang, Weiguo Wu, Jun Yang:
ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs. DATE 2018: 1247-1252 - 2016
- [j2]Jinhua Cui, Weiguo Wu, Nianjun Zou, Yinfeng Wang:
Accelerating master-slave databases launched on LDPC-induced solid state drives with improved efficiency and reliability. IEICE Electron. Express 13(13): 20160468 (2016) - [c4]Jinhua Cui, Weiguo Wu, Xingjun Zhang, Jianhang Huang, Yinfeng Wang:
Exploiting latency variation for access conflict reduction of NAND flash memory. MSST 2016: 1-7 - [c3]Jinhua Cui, Weiguo Wu, Shiqiang Nie, Jianhang Huang, Zhuang Hu, Nianjun Zou, Yinfeng Wang:
VIOS: A Variation-Aware I/O Scheduler for Flash-Based Storage Systems. NPC 2016: 3-16 - [c2]Jinhua Cui, Weiguo Wu, Shiqiang Nie, Jianhang Huang, Zhuang Hu, Nianjun Zou, Yinfeng Wang:
Exploiting Cross-Layer Hotness Identification to Improve Flash Memory System Performance. NPC 2016: 17-28 - 2014
- [j1]Jinhua Cui, Weiguo Wu, Yinfeng Wang, Zhangfeng Duan:
PT-LRU: a probabilistic page replacement algorithm for NAND flash-based consumer electronics. IEEE Trans. Consumer Electron. 60(4): 614-622 (2014) - [c1]Yuanquan Fan, Weiguo Wu, Yunlong Xu, Yangjie Cao, Qian Li, Jinhua Cui, Zhangfeng Duan:
Performance Prediction Model in Heterogeneous MapReduce Environments. CIT 2014: 240-245
Coauthor Index
aka: Laurence Tianruo Yang
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