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André Bannwart Perina

André B. Perina

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Journal Articles

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2021
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  - journals/tc/PerinaSBB21
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  - https://dblp.org/rec/journals/tc/PerinaSBB21
André B. Perina, Arthur Silitonga, Jürgen Becker, Vanderlei Bonato:
Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis. IEEE Trans. Computers 70(12): 2070-2082 (2021)
2014
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Marcilyanne Moreira Gois, Paulo Matias, André Bannwart Perina, Vanderlei Bonato, Alexandre C. B. Delbem:
A Parallel Hardware Architecture based on Node-Depth Encoding to Solve Network Design Problems. Int. J. Nat. Comput. Res. 4(1): 54-75 (2014)

Conference and Workshop Papers

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2019
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André Bannwart Perina, Jürgen Becker, Vanderlei Bonato:
ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis. ICECS 2019: 618-621
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André Bannwart Perina, Jürgen Becker, Vanderlei Bonato:
Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE. FPT 2019: 343-346
2018
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André Bannwart Perina, Vanderlei Bonato:
Mapping Estimator for OpenCL Heterogeneous Accelerators. FPT 2018: 294-297
2017
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André B. Perina, Paulo Matias, Eduardo Marques, Vanderlei Bonato, João Miguel Gago Pontes de Brito Lima:
Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA. DSD 2017: 516-519

Informal and Other Publications

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2014
[i1]
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André Bannwart Perina, Marcilyanne Moreira Gois, Paulo Matias, João M. P. Cardoso, Alexandre C. B. Delbem, Vanderlei Bonato:
Representation of Evolutionary Algorithms in FPGA Cluster for Project of Large-Scale Networks. CoRR abs/1412.5384 (2014)

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