default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDSD 2017: Vienna, Austria
- Hana Kubátová, Martin Novotný, Amund Skavhaug:
Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-2146-2
LPA: Low-Power Architectures and Design Methods
- Florian Neugebauer, Ilia Polian, John P. Hayes:
Building a Better Random Number Generator for Stochastic Computing. 1-8 - Dominik Macko
:
Rapid Estimation of Power-Management Unit Overhead from System-Level Specification. 9-13 - Kanishkan Vadivel, Mark Wijtvliet, Roel Jordans, Henk Corporaal:
Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures. 14-21 - Sidartha A. L. Carvalho, Daniel C. Cunha, Abel Guilhermino da Silva Filho:
Autonomous Power Management for Embedded Systems Using a Non-linear Power Predictor. 22-29
SMVS: Specification, Modeling, Verification and Simulation Methods and Tools
- Tobias Strauch:
An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL). 30-39 - Antoine Faravelon, Olivier Gruber, Frédéric Pétrot:
Optimizing Memory Access Performance Using Hardware Assisted Virtualization in Retargetable Dynamic Binary Translation. 40-46 - Hector Posadas, Luis Diaz, Eugenio Villar:
Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy. 47-53 - Laurence Pierre, Martial Chabot:
Assertion-Based Verification for SoC Models and Identification of Key Events. 54-61
RTHP: Advanced Applications, Real-Time and High-Performance Design
- Seungbum Jo, Markus Lohrey, Damian Ludwig, Simon Meckel, Roman Obermaisser, Simon Plasger:
An Architecture for Online-Diagnosis Systems Supporting Compressed Communication. 62-69 - Carlos Alberto Oliveira De Souza, Erinaldo Pereira, Eduardo Marques:
A Hardware/Software Codesign for the Chemical Reactivity of BRAMS. 70-77 - Marcel Beuler, Alexander Krum, Werner Bonath, Hartmut Hillmer:
Nepteron Processor for Real-Time Computation of Conductance-Based Neuronal Networks. 78-85 - Tobias Scheipel, Fabian Mauroner, Marcel Baunach:
System-Aware Performance Monitoring Unit for RISC-V Architectures. 86-93 - Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Leonardo Intesa:
SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs. 94-101 - Fabian Mauroner, Marcel Baunach:
EventIRQ: An Event Based and Priority Aware IRQ Handling for Multi-tasking Environments. 102-110 - Marko S. Andjelkovic, Vladimir Petrovic, Miljana Nenadovic, Anselm Breitenreiter, Milos Krstic, Rolf Kraemer:
Design of an On-chip System for the SET Pulse Width Measurement. 111-118 - Tobias Strauch:
Acceleration Techniques for System-Hyper-Pipelined Soft-Processors on FPGAs. 119-128
DSM: Design and Synthesis Methods
- Benjamin Carrión Schäfer, David Aledo, Félix Moreno:
Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study. 129-136 - Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco:
Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis. 137-144 - Adam Klimowicz:
Performance Targeted Minimization of Incompletely Specified Finite State Machines for Implementation in FPGA Devices. 145-150 - Alessandro Pappalardo, Giuseppe Natale, Marco Domenico Santambrogio:
A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains. 151-154 - Esko Pekkarinen, Mikko Teuho, Timo Hämäläinen:
Analysis and Visualization of Product Memory Layout in IP-XACT. 155-162 - Petr Fiser, Ivo Hálecek, Jan Schmidt:
SAT-Based Generation of Optimum Function Implementations with XOR Gates. 163-170 - Charles Effiong, Gilles Sassatelli, Abdoulaye Gamatié:
Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing. 171-178 - Michal Kekely, Jan Korenek:
Packet Classification with Limited Memory Resources. 179-183 - Hela Belhadj Amor, Abbas Sheibanyrad, Frédéric Pétrot:
A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support. 184-191 - Yves Durand, Christian Bernard, Romain Lemaire, César Fuguet Tortolero, Emilie Garat:
A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems. 192-197 - Merten Popp, Stef van Son, Orlando Moreira:
Automatic Control Flow Generation for OpenVX Graphs. 198-204
AHSA: Architectures and Hardware for Security Applications
- Hannes Groß, David Schaffenrath, Stefan Mangard:
Higher-Order Side-Channel Protected Implementations of KECCAK. 205-212 - Thomas Hiscock, Olivier Savry, Louis Goubin:
Lightweight Software Encryption for Embedded Processors. 213-220 - Apostolos P. Fournaris, Charalambos Dimopoulos, Odysseas G. Koufopavlou:
A Design Strategy for Digit Serial Multiplier Based Binary Edwards Curve Scalar Multiplier Architectures. 221-228 - Thomas Ulz, Thomas Pieber, Christian Steger, Sarah Haas, Rainer Matischek, Holger Bock:
Hardware-Secured Configuration and Two-Layer Attestation Architecture for Smart Sensors. 229-236 - Durga Prasad Sahoo, Phuong Ha Nguyen, Debapriya Basu Roy, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty:
Side Channel Evaluation of PUF-Based Pseudorandom Permutation. 237-243 - Sergei Skorobogatov:
How Microprobing Can Attack Encrypted Memory. 244-251 - Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Rodrigo Possamai Bastos, Philippe Maurine:
Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation. 252-259 - Jan Riha, Vojtech Miskovský, Hana Kubátová, Martin Novotný:
Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of Cryptographic Design. 260-267 - Lampros Pyrgas, Filippos Pirpilidis, Aliki Panayiotarou, Paris Kitsos:
Thermal Sensor Based Hardware Trojan Detection in FPGAs. 268-273 - Sanjay Deshpande, Kris Gaj:
Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates. 274-282
AHSA-Posters
- Pallabi Ghosh, Rajat Subhra Chakraborty:
Counterfeit IC Detection By Image Texture Analysis. 283-286 - Fotios Kounelis, Nicolas Sklavos, Paris Kitsos:
Run-Time Effect by Inserting Hardware Trojans, in Combinational Circuits. 287-290 - Maryam Ehsanpour, Stelvio Cimato, Valentina Ciriani, Ernesto Damiani:
Exploiting Quantum Gates in Secure Computation. 291-294 - Johan Marconot, Florian Pebay-Peyroula, David Hély:
IoT Components LifeCycle Based Security Analysis. 295-298
DTFT: Dependability, Testing and Fault Tolerance in Digital Systems
- Louis D. van Harten, Roel Jordans, Hamid Reza Pourshaghaghi:
Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case Study. 299-306 - Robert Hülle, Petr Fiser, Jan Schmidt:
SAT-Based ATPG for Zero-Aliasing Compaction. 307-314 - Sören Schreiner, Maher Fakih, Kim Grüttner, Duncan Graham, Wolfgang Nebel, Salvador Peiro Frasquet:
A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms. 315-322 - Alireza Namazi, Meisam Abdollahi:
PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files. 323-328 - Bernhard Fritz, Andreas Steininger, Václav Simek, Varadan Savulimedu Veeravalli:
Setup for an Experimental Study of Radiation Effects in 65nm CMOS. 329-336 - Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek:
Reliability Analysis and Improvement of FPGA-Based Robot Controller. 337-344 - Warin Sootkaneung, Suppachai Howimanporn, Sasithorn Chookaew:
Thermal Effect on Performance, Power, and BTI Aging in FinFET-Based Designs. 345-351
DTFT-Posters
- Josef Strnadel:
On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. 352-355 - Ondrej Cekan, Zdenek Kotásek:
A Probabilistic Context-Free Grammar Based Random Test Program Generation. 356-359 - Martin Danhel, Filip Stepánek, Hana Kubátová:
Dependability Prediction Involving Temporal Redundancy and the Effect of Transient Faults. 360-363 - Alireza Namazi, Meisam Abdollahi, Saeed Safari, Siamak Mohammadi:
LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time Applications. 364-367
ASAIT: Architectures and Systems for Automotive and Intelligent Transportation
- Josef Steinbaeck, Allan Tengg, Gerald Holweg, Norbert Druml:
A 3D Time-of-Flight Mixed-Criticality System for Environment Perception. 368-374 - Dharshan Krishna Murthy, Alejandro Masrur:
A Subplatooning Strategy for Safe Braking Maneuvers. 375-382 - Selma Saidi:
On the Benefits of Multicores for Real-Time Systems. 383-389 - Rabie Ben Atitallah, Karim M. A. Ali:
FPGA-Centric High Performance Embedded Computing: Challenges and Trends. 390-395
SDIS: System Design for Intelligent Systems
- Emad Ebeid, Martin Skriver, Jie Jin:
A Survey on Open-Source Flight Control Platforms of Unmanned Aerial Vehicle. 396-402 - Rune Hylsberg Jacobsen, Jacob Hoxbroe Jeppesen, Kim Fibiger Laursen, John Skovsgaard, Henrik Nymann Jensen, Thomas Skjødeberg Toftegaard:
A Scalable Cloud Computing Infrastructure for Geospatial Data Analytics for Change Detection. 403-410 - Jacob Theilgaard Madsen, Tomasz Minko, Tatiana K. Madsen, Hans-Peter Schwefel:
Evaluating the Impact of Communication Network Performance on Supervisory Supermarket Control. 411-418
MCSDIA: Mixed Criticality System Design, Implementation and Analysis
- Asier Larrucea, Imanol Martinez, Carlos Fernando Nicolás, Jon Pérez, Roman Obermaisser:
Modular Development and Certification of Dependable Mixed-Criticality Systems. 419-426 - Federico Reghenzani, Giuseppe Massari, William Fornaciari:
Mixed Time-Criticality Process Interferences Characterization on a Multicore Linux System. 427-434
MCSDIA-Posters
- Mahmoud Hussein, Ansgar Radermacher, Réda Nouacer:
Model-Based Function Mapping and Bandwidth Reservation for Mixed-Critical Adaptive Systems. 435-439 - Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis. 440-444
ASHWPA: Advanced Systems in Healthcare, Wellness and Personal Assistance
- Emanuele Torti, Camilla Cividini, Alessandro Gatti, Giovanni Danese, Francesco Leporati, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó:
The HELICoiD Project: Parallel SVM for Brain Cancer Classification. 445-450 - Quentin Angermann, Aymeric Histace, Maroua Hammami, Mehdi Terosiet, Lionel Faurlini, Olivier Romain:
Hardware Platforms Benchmark For Real-Time Polyp Detection. 451-455 - Edwin De Roux, Mehdi Terosiet, Florian Kölbl, Johnatan Chrun, Pierre-Henry Aubert, Philippe Banet, Michel Boissière, Emmanuel Pauthe, Aymeric Histace, Olivier Romain:
Wireless and Portable System for the Study of in-vitro Cell Culture Impedance Spectrum by Electrical Impedance Spectroscopy. 456-461 - Florian Glaser, Philipp Schönle, Pascale Meier, Jonathan Bosser, Noé Brun, Thomas Burger, Schekeb Fateh, Giovanni Rovere, Luca Benini, Qiuting Huang:
Towards a Mobile Health Platform with Parallel Processing and Multi-sensor Capabilities. 462-469
EPDSD: European Projects in Digital System Design
- Mahmoud Hussein, Réda Nouacer, Ansgar Radermacher:
Towards a Safe Software Development Environment. 470-477 - José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni:
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. 478-485 - Alvise Rigo, Christian Pinto, Kevin Pouget, Daniel Raho, Denis Dutoit, Pierre-Yves Martinez, Chris Doran, Luca Benini, Iakovos Mavroidis, Manolis Marazakis, Valeria Bartsch, Guy Lonsdale, Antoniu Pop, John Goodacre, Annaik Colliot, Paul M. Carpenter, Petar Radojkovic, Dirk Pleiter, Dominique Drouin, Benoît Dupont de Dinechin:
Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach. 486-493 - Wasif Afzal, Hugo Bruneliere, Davide Di Ruscio, Andrey Sadovykh, Silvia Mazzini, Eric Cariou, Dragos Truscan, Jordi Cabot, Daniel Field, Luigi Pomante, Pavel Smrz:
The MegaM@Rt2 ECSEL Project: MegaModelling at Runtime - Scalable Model-Based Framework for Continuous Development and Runtime Validation of Complex Systems. 494-501 - Nicolas Sklavos, Ioannis D. Zaharakis, Achilles Kameas, Angeliki Kalapodi:
Security & Trusted Devices in the Context of Internet of Things (IoT). 502-509 - Roberto Ammendola, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Piero Vicini, Giuliano Taffoni, Jose Antonio Pascual, Javier Navaridas, Mikel Luján, John Goodacre, Nikolaos Chrysos, Manolis Katevenis:
The Next Generation of Exascale-Class Systems: The ExaNeSt Project. 510-515
Main-Posters
- André B. Perina, Paulo Matias, Eduardo Marques, Vanderlei Bonato, João Miguel Gago Pontes de Brito Lima:
Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA. 516-519 - Ricardo de Porras Bernacer:
Designing a Synthetic Aperture Radar's Data Formatting and Antenna Gyro Stabilizing Module. 520-523 - Mina Niknafs, Ivan Ukhov, Petru Eles, Zebo Peng:
Two-Phase Interarrival Time Prediction for Runtime Resource Management. 524-528 - Pedro Trancoso, Michalis Efstathiou:
Low-Cost Sub-5W Processors for Edge HPC. 529-532 - Matthias Göbel, Ahmed Elhossini, Ben H. H. Juurlink:
A Methodology for Predicting Application-Specific Achievable Memory Bandwidth for HW/SW-Codesign. 533-537 - Ihsen Alouani, Thomas Wild, Andreas Herkersdorf, Smaïl Niar:
Adaptive Reliability for Fault Tolerant Multicore Systems. 538-542 - Mercedeh Sanjabi, Ali Jahanian, Maryam Tahmasebi:
High-Performance General-Purpose Arithmetic Operations Using the Massive Parallel DNA-Based Computation. 543-546 - Aniseh Dorostkar, Arghavan Asad, Mahmood Fathy, Farah Mohammadi:
Optimal Placement of Heterogeneous Uncore Component in 3D Chip-Multiprocessors. 547-551
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-05-17 00:34 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
