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ORCIDYe Zhang 0011
Person information
- affiliation: Fudan University, State Key Laboratory of ASIC and Systems, Shanghai, China
Other persons with the same name
- Ye Zhang — disambiguation page
- Ye Zhang 0001 — Penn State University (and 1 more)
- Ye Zhang 0002 — Technical University of Denmark, Lyngby
- Ye Zhang 0003
![[0000-0001-7783-6584]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-7783-6584")
— RWTH Aachen University, Germany - Ye Zhang 0004 — University of Tokyo
- Ye Zhang 0005 — University of Illinois at Urbana-Champaign, IL, USA
- Ye Zhang 0006 — Nanchang University, Nanchang, China
- Ye Zhang 0007 — National University of Defense Technology, College of Electronic Science, Changsha, China
- Ye Zhang 0008 — Harbin Institute of Technology, School of Electronics and Information Engineering, China
- Ye Zhang 0009 — East China University of Science and Technology, Shanghai, China
- Ye Zhang 0010 — Hohai University, College of Computer and Information, Nanjing, China
- Ye Zhang 0012 — Xi'an Polytechnic University, China (and 1 more)
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Journal Articles
- 2018
[j3]Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng:
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1613-1626 (2018)- 2015
- [j2]Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng:
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. ACM Trans. Design Autom. Electr. Syst. 21(1): 2:1-2:25 (2015) - 2014
- [j1]Xingbao Zhou, Fan Yang, Hai Zhou, Min Gong, Hengliang Zhu, Ye Zhang, Xuan Zeng:
Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(11): 2227-2235 (2014)
Conference and Workshop Papers
- 2017
- [c3]Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng:
Network flow based cut redistribution and insertion for advanced 1D layout design. ASP-DAC 2017: 360-365 - [c2]Ye Zhang, Fan Yang, Dian Zhou, Xuan Zeng, Xiangdong Hu:
A grid-based detailed routing algorithm for advanced 1D process. ISCAS 2017: 1-4 - 2013
- [c1]Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng:
Layout decomposition with pairwise coloring for multiple patterning lithography. ICCAD 2013: 170-177
Coauthor Index
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