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ORCIDS. Balamurugan 0001
Person information
- affiliation: Vellore Institute of Technology, India
Other persons with the same name
- S. Balamurugan — disambiguation page
- S. Balamurugan 0002
![[0000-0002-9437-3662]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-9437-3662")
— Annamalai University, Chidambaram, India
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2020 – today
- 2023
[j6]Paramanand Prajapati, S. Balamurugan:
Leveraging GaN for DC-DC Power Modules for Efficient EVs: A Review. IEEE Access 11: 95874-95888 (2023)- [j5]Saikumar Bairabathina, S. Balamurugan:
Design, prototype validation, and reliability analysis of a multi-input DC/DC converter for grid-independent hybrid electric vehicles. Int. J. Circuit Theory Appl. 51(5): 2375-2405 (2023) - 2022
- [j4]Aakash Choudhury, Arjav Choudhury, Umashankar Subramanium, S. Balamurugan:
HealthSaver: a neural network based hospital recommendation system framework on flask webapplication with realtime database and RFID based attendance system. J. Ambient Intell. Humaniz. Comput. 13(10): 4953-4966 (2022)
2010 – 2019
- 2019
- [c5]Gowthamaraj Rajendran, R. S. Ragul Nivash, Purushotham Parthiban Parthy, S. Balamurugan:
Modern security threats in the Internet of Things (IoT): Attacks and Countermeasures. ICCST 2019: 1-6 - 2018
- [j3]R. Marimuthu, S. Balamurugan, Partha Sharathi Mallick:
Design of 5-3 multicolumn compressor for high performance multiplier. Int. J. Comput. Aided Eng. Technol. 10(5): 568-575 (2018) - [c4]Saurabh Kumar, R. Marimuthu, S. Balamurugan:
Design and Analysis of 4-Bit Squarer Circuit Using Minority and Majority Logic in MagCAD. SocProS (2) 2018: 409-417 - [c3]Raunak R. Lahoti, Shantanu Agarwal, S. Balamurugan, R. Marimuthu:
Realization of 2-D DCT Using Adder Compressor. SocProS (2) 2018: 575-580 - [c2]Shantanu Agarwal, G. Harish, S. Balamurugan, R. Marimuthu:
Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic. VDAT 2018: 49-60 - 2017
- [j2]S. Balamurugan, Partha Sharathi Mallick:
Error Compensation Techniques for Fixed-Width Array Multiplier Design - A Technical Survey. J. Circuits Syst. Comput. 26(3): 1730003:1-1730003:31 (2017) - 2012
- [j1]S. Balamurugan, Sneha Ghosh, Atul, Balakumaran Srirangaswamy, R. Marimuthu, Partha Sharathi Mallick:
Design of low power fixed-width multiplier with row bypassing. IEICE Electron. Express 9(20): 1568-1575 (2012) - [c1]S. Balamurugan, Balakumaran Srirangaswamy, R. Marimuthu, Partha Sharathi Mallick:
FPGA design and implementation of truncated multipliers using bypassing technique. ICACCI 2012: 1111-1117
Coauthor Index
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