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Yirng-An Chen
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Journal Articles
- 2001
- [j3]Randal E. Bryant, Yirng-An Chen:
Verification of arithmetic circuits using binary moment diagrams. Int. J. Softw. Tools Technol. Transf. 3(2): 137-155 (2001) - [j2]Yirng-An Chen, Randal E. Bryant:
An efficient graph representation for arithmetic circuitverification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1443-1454 (2001) - 1992
- [j1]Yirng-An Chen, Youn-Long Lin, Long-Wen Chang:
A Systolic Algorithm for the k-Nearest Neighbors Problem. IEEE Trans. Computers 41(1): 103-108 (1992)
Conference and Workshop Papers
- 2003
- [c9]Yirng-An Chen, Fang-Sung Chen:
Algorithms for compacting error traces. ASP-DAC 2003: 99-103 - [c8]Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai:
Advanced techniques for RTL debugging. DAC 2003: 362-367 - 2001
- [c7]Jiunn-Chern Chen, Yirng-An Chen:
Equivalence checking of integer multipliers. ASP-DAC 2001: 169-174 - 1998
- [c6]Bwolen Yang, Yirng-An Chen, Randal E. Bryant, David R. O'Hallaron:
Space- and Time-Efficient BDD Construction via Working Set Control. ASP-DAC 1998: 423-432 - [c5]Yirng-An Chen, Randal E. Bryant:
Verification of Floating-Point Adders. CAV 1998: 488-499 - 1997
- [c4]Yirng-An Chen, Randal E. Bryant:
PHDD: an efficient graph representation for floating point circuit verification. ICCAD 1997: 2-7 - 1996
- [c3]Yirng-An Chen, Edmund M. Clarke, Pei-Hsin Ho, Yatin Vasant Hoskote, Timothy Kam, Manpreet Khaira, John W. O'Leary, Xudong Zhao:
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking. FMCAD 1996: 19-33 - [c2]Yirng-An Chen, Randal E. Bryant:
ACV: an arithmetic circuit verifier. ICCAD 1996: 361-365 - 1995
- [c1]Randal E. Bryant, Yirng-An Chen:
Verification of Arithmetic Circuits with Binary Moment Diagrams. DAC 1995: 535-541
Coauthor Index
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