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2010 – 2019
- 2013
[c15]Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava
, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest:
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. DAC 2013: 24:1-24:6- 2012
- [c14]Esteve Amat, A. Asenov, Ramon Canal, Binjie Cheng, J.-Ll. Cruz, Zoran Jaksic, Miguel Miranda, Antonio Rubio, Paul Zuber:
Analysis of FinFET technology on memories. IOLTS 2012: 169 - 2011
- [c13]Petr Dobrovolný, Miguel Miranda, Paul Zuber:
Variability Aware Sub-Wavelength Lithography Characterization for Robust SRAM Design. ARCS Workshops 2011 - [c12]Miguel Miranda, Paul Zuber, Petr Dobrovolný, Philippe Roussel:
Variability aware modeling for yield enhancement of SRAM and logic. DATE 2011: 1153-1158 - [c11]Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanausú Ramírez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber:
New reliability mechanisms in memory design for sub-22nm technologies. IOLTS 2011: 111-114 - [c10]Ramon Canal, Antonio Rubio, A. Asenov, A. Brown, Miguel Miranda, Paul Zuber, Antonio González, Xavier Vera:
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies. FET 2011: 148-149 - 2010
- [j2]Peter Gritzmann, Michael Ritter, Paul Zuber:
Optimal wire ordering and spacing in low power semiconductor design. Math. Program. 121(2): 201-220 (2010) - [c9]Paul Zuber, Petr Dobrovolný, Miguel Miranda:
A holistic approach for statistical SRAM analysis. DAC 2010: 717-722 - [c8]Paul Zuber, Miguel Miranda, Petr Dobrovolný, Koen van der Zanden, Jong-Hoon Jung:
Statistical SRAM analysis for yield enhancement. DATE 2010: 57-62
2000 – 2009
- 2009
- [j1]Paul Zuber, Othman Bahlous, Thomas Ilnseher, Michael Ritter, Walter Stechele:
Wire Topology Optimization for Low Power CMOS. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 1-11 (2009) - [c7]Miguel Miranda, Bart Dierickx, Paul Zuber, Petr Dobrovolný, F. Kutscherauer, Philippe Roussel, Pavel Poliakov:
Variability aware modeling of SoCs: From device variations to manufactured system yield. ISQED 2009: 547-553 - [c6]Paul Zuber, Vladimir Matvejev, Philippe Roussel, Petr Dobrovolný, Miguel Miranda:
Exponent Monte Carlo for Quick Statistical Circuit Simulation. PATMOS 2009: 36-45 - 2005
- [c5]Paul Zuber, Armin Windschiegl, Raúl Medina Beltrán de Otálora, Walter Stechele, Andreas Herkersdorf:
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. DATE 2005: 986-987 - [c4]Paul Zuber, Florian Helmut Müller, Walter Stechele:
Optimization Potential of CMOS Power by Wire Spacing. GI Jahrestagung (1) 2005: 344-348 - [c3]Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele:
The Optimal Wire Order for Low Power CMOS. PATMOS 2005: 674-683 - 2002
- [c2]Armin Windschiegl, Torsten Mahnke, Michael Eiermann, Walter Stechele, Paul Zuber:
A wire load model considering metal layer properties. ICECS 2002: 765-768 - [c1]Armin Windschiegl, Paul Zuber, Walter Stechele:
Exploiting Metal Layer Characteristics for Low-Power Routing. PATMOS 2002: 55-64
Coauthor Index
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