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2010 – 2019
- 2013
[c12]Martin Keim, Tom Waayers, Richard Morren, Friedrich Hapke, Rene Krenz-Baath:
Industrial Application of IEEE P1687 for an Automotive Product. DSD 2013: 453-461- 2010
- [c11]Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab:
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC 2010: 114-123
2000 – 2009
- 2005
- [c10]Tom Waayers, Erik Jan Marinissen
, Maurice Lousberg:
IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. Asian Test Symposium 2005: 450 - [c9]Tom Waayers, Richard Morren, Roberto Grandi:
Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain. ITC 2005: 10 - 2004
- [c8]Erik Jan Marinissen, Tom Waayers:
Infrastructure for modular SOC testing. CICC 2004: 671-678 - [c7]Geert Seuren, Tom Waayers:
Extending the Digital Core-based Test Methodology to Support Mixed-Signal. ITC 2004: 281-289 - 2003
- [j2]Bart Vermeulen, Tom Waayers, Sjaak Bakker:
Multi-TAP Controller Architecture for Digital System Chips. J. Electron. Test. 19(4): 417-424 (2003) - [c6]Leon van de Logt, Frank van der Heyden, Tom Waayers:
An extension to JTAG for at-speed debug on a system. ITC 2003: 785-792 - [c5]Tom Waayers:
An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips. ITC 2003: 1145-1154 - 2002
- [j1]Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier:
Enhanced Reduced Pin-Count Test for Full-Scan Design. J. Electron. Test. 18(2): 129-143 (2002) - [c4]Bart Vermeulen, Tom Waayers, Sjaak Bakker:
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. ITC 2002: 55-63 - [c3]Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel:
Core-Based Scan Architecture for Silicon Debug. ITC 2002: 638-647 - 2001
- [c2]Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier:
Enhanced reduced pin-count test for full-scan design. ITC 2001: 738-747 - [c1]Sandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswara:
A P1500 Compliant Programable BistShell for Embedded Memories. MTDT 2001: 21-28
Coauthor Index
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