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ORCIDAnirudh Iyengar
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2020 – today
- 2023
[i2]Seyedhamidreza Motaman, Swaroop Ghosh, Jae-Won Jang, Anirudh Iyengar, Rekha Govindaraj, Zakir Khondker:
A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays. CoRR abs/2306.03972 (2023)- 2020
- [j8]Jae-Won Jang
, Asmit De, Deepak Vontela, Ithihasa Reddy Nirmala, Swaroop Ghosh, Anirudh Iyengar:
Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 308-320 (2020)
2010 – 2019
- 2018
- [j7]Anirudh Srikant Iyengar, Swaroop Ghosh, Nitin Rathi:
Magnetic Tunnel Junction Reliability Assessment Under Process Variations and Activity Factors and Mitigation Techniques. J. Low Power Electron. 14(2): 217-226 (2018) - [j6]Mohammad Nasim Imtiaz Khan, Anirudh Iyengar, Swaroop Ghosh:
Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing of STTRAM. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1508-1517 (2018) - [c9]Asmit De, Anirudh Iyengar, Mohammad Nasim Imtiaz Khan, Sung-Hao Lin, Sandeep Krishna Thirumala, Swaroop Ghosh, Sumeet Kumar Gupta:
CTCG: Charge-trap based camouflaged gates for reverse engineering prevention. HOST 2018: 103-110 - [c8]Anirudh Srikant Iyengar, Deepak Vontela, Ithihasa Reddy Nirmala, Swaroop Ghosh, Seyedhamidreza Motaman, Jae-Won Jang:
Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection. ISLPED 2018: 6:1-6:6 - 2017
- [c7]Mohammad Nasim Imtiaz Khan, Anirudh Srikant Iyengar, Swaroop Ghosh:
Novel magnetic burn-in for retention testing of STTRAM. DATE 2017: 666-669 - 2016
- [j5]Anirudh Iyengar, Swaroop Ghosh, Srikant Srinivasan:
Retention Testing Methodology for STTRAM. IEEE Des. Test 33(5): 7-15 (2016) - [j4]Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar:
Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 265-278 (2016) - [j3]Anirudh Iyengar, Swaroop Ghosh, Kenneth Ramclam, Jae-Won Jang, Cheng-Wei Lin:
Spintronic PUFs for Security, Trust, and Authentication. ACM J. Emerg. Technol. Comput. Syst. 13(1): 4:1-4:15 (2016) - [c6]Nitin Rathi, Swaroop Ghosh, Anirudh Iyengar, Helia Naeimi:
Data privacy in non-volatile cache: Challenges, attack models and solutions. ASP-DAC 2016: 348-353 - [c5]Anirudh Iyengar, Swaroop Ghosh, Nitin Rathi, Helia Naeimi:
Side channel attacks on STTRAM and low-overhead countermeasures. DFT 2016: 141-146 - [c4]Ithihasa Reddy Nirmala, Deepak Vontela, Swaroop Ghosh, Anirudh Iyengar:
A novel threshold voltage defined switch for circuit camouflaging. ETS 2016: 1-2 - 2015
- [j2]Anirudh Srikant Iyengar, Swaroop Ghosh, Kenneth Ramclam:
Domain Wall Magnets for Embedded Memory and Hardware Security. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 40-50 (2015) - [j1]Anirudh Srikant Iyengar, Swaroop Ghosh, Jae-Won Jang:
MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2062-2068 (2015) - [i1]Anirudh Iyengar, Swaroop Ghosh:
Threshold Voltage-Defined Switches for Programmable Gates. CoRR abs/1512.01581 (2015) - 2014
- [c3]Anirudh Iyengar, Swaroop Ghosh:
Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory. DAC 2014: 65:1-65:6 - [c2]Anirudh Iyengar, Kenneth Ramclam, Swaroop Ghosh:
DWM-PUF: A low-overhead, memory-based security primitive. HOST 2014: 154-159 - [c1]Seyedhamidreza Motaman, Anirudh Iyengar, Swaroop Ghosh:
Synergistic circuit and system design for energy-efficient and robust domain wall caches. ISLPED 2014: 195-200
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