Yih-Lang Li

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Hidetoshi Onodera

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Publications

2022
[j19]
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Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5568-5581 (2022)
2021
[j18]
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  - journals/ipsj/NishizawaLLO21
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Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera:
Supplemental PDK for ASAP7 Using Synopsys Flow. IPSJ Trans. Syst. LSI Des. Methodol. 14: 24-26 (2021)
2020
[c44]
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  - conf/iccad/LiLNO20
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Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera:
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. ICCAD 2020: 157:1-157:8
2019
[c41]
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  - conf/dac/LiLNSFCO19
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Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. DAC 2019: 120
2017
[c32]
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  - conf/socc/SuNWSLO17
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  - https://dblp.org/rec/conf/socc/SuNWSLO17
Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera:
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC 2017: 56-61

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