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"Pin accessibility evaluating model for improving routability of VLSI designs."

Hong-Yan Su et al. (2017)

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DOI: 10.1109/SOCC.2017.8226007

access: closed

type: Conference or Workshop Paper

metadata version: 2017-12-22

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  dblp key:
  - conf/socc/SuNWSLO17
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  - https://dblp.org/rec/conf/socc/SuNWSLO17
Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera:
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC 2017: 56-61

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