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ORCIDManoranjan Satpathy
- > Home > Persons > Manoranjan Satpathy
Publications
- 2023
[j18]Shivani Tripathy
, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam:
Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2766-2770 (2023)- 2020
- [c37]Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam:
Fuzzy fairness controller for NVMe SSDs. ICS 2020: 22:1-22:12 - [c36]Devashree Tripathy, Hadi Zamani, Debiprasanna Sahoo, Laxmi N. Bhuyan, Manoranjan Satpathy:
Slumber: static-power management for GPGPU register files. ISLPED 2020: 109-114 - 2019
- [j14]Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop:
Formal Modeling and Verification of a Victim DRAM Cache. ACM Trans. Design Autom. Electr. Syst. 24(2): 20:1-20:23 (2019) - [c35]Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam:
Post-Model Validation of Victim DRAM Caches. ICCD 2019: 305-308 - [c34]Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Srinivas Pinisetty:
Formal Modeling and Verification of NAND Flash Memory Supporting Advanced Operations. ICCD 2019: 313-316 - [c33]Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy:
Multidimensional Grid Aware Address Prediction for GPGPU. VLSID 2019: 263-268 - 2018
- [j13]Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam:
ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. IEEE Comput. Archit. Lett. 17(2): 213-216 (2018) - [j12]Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop:
Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2485-2496 (2018) - [c32]Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan:
CAMO: A novel cache management organization for GPGPUs. ASP-DAC 2018: 215-220 - [c31]Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy:
DRAM cache access optimization leveraging line locking in tag cache: work-in-progress. CASES 2018: 12:1-12:3 - 2017
- [c30]Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam:
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors. VLSID 2017: 35-40 - 2016
- [c28]Debiprasanna Sahoo, Manoranjan Satpathy:
MSimDRAM: Formal Model Driven Development of a DRAM Simulator. VLSID 2016: 597-598
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